CONTROL OF ROUTER IN CLOUD SYSTEM

• US 20160239313A1
• Filed: 11/08/2013
• Published: 08/18/2016
• Est. Priority Date: 11/08/2013
• Status: Abandoned Application

• Current Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Original Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Inventors: KURABAYASHI, Shuichi
• Application Number:
  US14/384,979
• Publication Number:
  US 20160239313A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 9/4405 Initialisation of multiprocessor systems
• CPC Class Codes: G06F 9/4416 Network booting; Remote initial program loading [RIPL]
• CPC Class Codes: H04L 49/15 Interconnection of switching modules
• CPC Class Codes: H04L 49/20 Support for services

Abstract

Technologies are generally described for a scheme for controlling rebooting process of computing nodes. In some examples, a method performed under control of a router connected between a storage and a computing node may include receiving a signal that initiates a rebooting process of the computing node; enabling an FPGA (Field-Programmable Gate Array) to transmit at least one packet; and transmitting the at least one packet from the storage to the computing node based at least in part on a predefined FPGA program that is stored in the FPGA.

Claims

1. A method performed under control of a router connected between a storage and a computing node, comprising:

receiving a signal that initiates a rebooting process of the computing node;

enabling an FPGA (Field-Programmable Gate Array) to transmit at least one packet;

switching from a router ASIC (Application Specific Integrated Circuit) to the FPGA based on receiving the signal that initiates the rebooting process; and

transmitting the at least one packet from the storage to the computing node based at least in part on a predefined FPGA program that is stored in the FPGA.

2. The method of claim 1, further comprising:

switching from a router ASIC (Application Specific Integrated Circuit) to the FPGA,

wherein the router ASIC performs a normal routing process including at least one calculating process.

3. The method of claim 1, wherein the predefined FPGA program defines a one-to-one correspondence between the storage and the computing node.

4. The method of claim 3, wherein a MAC address of the storage is associated with a MAC address of the computing node in the predefined FPGA program.

5. The method of claim 3, further comprising:

generating the predefined FPGA program;

transmitting the predefined FPGA program to the FPGA; and

writing the predefined FPGA program into the FPGA.

6. The method of claim 3, further comprising:

receiving the predefined FPGA program; and

writing the predefined FPGA program into the FPGA.

7. The method of claim 1, wherein the storage is configured to store booting information of an operating system of the computing node, and

wherein the booting information is transmitted via the at least one packet from the storage to the computing node.

8. The method of claim 1, wherein the transmitting is performed between an Ethernet socket of the storage and an Ethernet socket of the computing node.

9. A router connected between a storage and a computing node, the router comprising:

an FPGA (Field-Programmable Gate Array) configured to transmit at least one packet from the storage to the computing node based at least in part on a predefined FPGA program that is stored in the FPGA; and

a switch configured to;

receive a signal that initiates a rebooting process of the computing node,

switch from a router ASIC (Application Specific Integrated Circuit) to the FPGA based on receiving the signal that initiates the rebooting process, and

enable the FPGA to transmit the at least one packet.

10. The router of claim 9, further comprising:

a router ASIC (Application Specific Integrated Circuit) configured to perform a normal routing process that includes at least one calculating process.

11. The router of claim 9, wherein the predefined FPGA program defines a one-to-one correspondence between the storage and the computing node.

12. The router of claim 11, wherein a MAC address of the storage is associated with a MAC address of the computing node in the predefined FPGA program.

13. The router of claim 11, further comprising:

an FPGA program generating unit configured to;

generate the predefined FPGA program, and

transmit the generated predefined FPGA program to the FPGA,

wherein the FPGA is further configured to;

receive the predefined FPGA program from the FPGA program generating unit, and

write the received predefined FPGA program into the FPGA.

14. The router of claim 13, further comprising:

a database configured to store storage information regarding a plurality of storages and computing node information regarding a plurality of computing nodes,

wherein the FPGA program generating unit is configured to generate, based on the storage information and the computing node information, the predefined FPGA program that defines a plurality of one-to-one correspondences between each of the plurality of storages and each of the plurality of computing nodes.

15. The router of claim 11, wherein the FPGA is further configured to:

receive the predefined FPGA program from a FPGA program generator that is operatively coupled to the router, and

write the received predefined FPGA program into the FPGA.

16. The router of claim 9, wherein the storage is configured to store booting information of an operating system of the computing node, and

wherein the FPGA is further configured to transmit the booting information from the storage to the computing node via the at least one packet.

17. The router of claim 9, wherein the FPGA is further configured to transmit the at least one packet from an Ethernet socket of the storage to an Ethernet socket of the computing node.

18. A computer-readable storage medium having stored thereon computer-executable instructions that, in response to execution, cause a router to perform operations, comprising:

receiving a signal that initiates a rebooting process regarding a computing node;

enabling an FPGA (Field-Programmable Gate Array) to transmit at least one packet;

switching from a router ASIC (Application Specific Integrated Circuit) to the FPGA based on receiving the signal that initiates the rebooting process; and

transmitting the at least one packet from a storage to the computing node based at least in part on a predefined FPGA program that is stored in the FPGA,

wherein the router is connected between the storage and the computing node.

19. The computer-readable storage medium of claim 18,

wherein the router ASIC performs a normal routing process including at least one calculating process.

20. The computer-readable storage medium of claim 19, wherein the storage is configured to store booting information of an operating system of the computing node, and

wherein the booting information is transmitted via the at least one packet from the storage to the computing node.