SYSTEM AND METHOD FOR PERIPHERAL BUS DEVICE FAILURE MANAGEMENT

• US 20160239371A1
• Filed: 02/16/2015
• Published: 08/18/2016
• Est. Priority Date: 02/16/2015
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Giannoules, James Peter, Jose, Cyril
• Granted Patent: US 10,114,688 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40

Abstract

A system and method for managing peripheral device failures is disclosed. The method includes detecting, at a processor of a peripheral bus, a failure of a first bus device at a downstream port from the processor. The downstream port is populated by the first bus device and the processor is communicatively coupled at an upstream port to a root complex. The processor is configured to isolate the failure of the first bus device from the root complex. The method also includes, responsive to detecting the failure, suspending communication of data to the first bus device, receiving information regarding a second bus device selected from a cluster of a plurality of bus devices, and assigning the second bus device to the downstream port.

Claims

1. A method for managing peripheral device failures, comprising:

detecting, at a processor of a peripheral bus, a failure of a first bus device at a downstream port from the processor, wherein the downstream port is populated by the first bus device, wherein the processor is communicatively coupled at an upstream port to a root complex and the processor is configured to isolate the failure of the first bus device from the root complex; and

responsive to detecting the failure;

suspending communication of data to the first bus device;

receiving information regarding a second bus device selected from a cluster of a plurality of bus devices; and

assigning the second bus device to the downstream port.

2. The method of claim 1, wherein the processor includes an arbitration entity and a management module.

3. The method of claim 1, wherein the cluster of the plurality of bus devices includes the first bus device.

4. The method of claim 1, wherein the cluster of the plurality of bus devices are bus devices of a similar type.

5. The method of claim 1, wherein the second bus device is selected by a management module communicatively coupled to the processor.

6. The method of claim 1, wherein suspending communication of data includes returning transaction layer packets (TLPs) to the root complex.

7. The method of claim 6, wherein returning TLPs to the root complex includes transmitting a request for retry notification.

8. The method of claim 1, wherein the peripheral bus is a peripheral component interconnect express bus.

9. The method of claim 8, wherein suspending communication of data includes using data link layer packet (DLLP) flow control.

10. An information handling system for managing peripheral device failures comprising:

a processor for a peripheral bus, the processor configured to;

detect a failure of a first bus device at a downstream port from the processor, wherein the downstream port is populated by the first bus device, wherein the processor is communicatively coupled at an upstream port to a root complex and the processor is configured to isolate the failure of the first bus device from the root complex; and

responsive to detecting the failure;

suspend communication of data to the first bus device;

receive information regarding a second bus device selected from a cluster of a plurality of bus devices; and

assign the second bus device to the downstream port.

11. The information handling system of claim 10, wherein the processor includes an arbitration entity and a management module.

12. The information handling system of claim 10, wherein the cluster of the plurality of bus devices includes the first bus device.

13. The information handling system of claim 10, wherein the cluster of the plurality of bus devices are bus devices of a similar type.

14. The information handling system of claim 10, wherein the second bus device is selected by a management module communicatively coupled to the processor.

15. The information handling system of claim 10, wherein suspending communication of data includes returning transaction layer packets (TLPs) to the root complex.

16. The information handling system of claim 15, wherein returning TLPs to the root complex includes transmitting a request for retry notification.

17. A non-transitory computer-readable medium storing instructions, that, when executed by a processor, cause the processor to:

detect a failure of a first bus device at a downstream port from the processor, wherein the downstream port is populated by the first bus device, wherein the processor is communicatively coupled at an upstream port to a root complex and the processor is configured to isolate the failure of the first bus device from the root complex; and

responsive to detecting the failure;

suspend communication of data to the first bus device;

receive information regarding a second bus device selected from a cluster of a plurality of bus devices; and

assign the second bus device to the downstream port.

18. The non-transitory computer-readable medium of claim 17, wherein the processor includes an arbitration entity and a management module.

19. The non-transitory computer-readable medium of claim 17, wherein the cluster of the plurality of bus devices includes the first bus device.

20. The non-transitory computer-readable medium of claim 17, wherein the cluster of the plurality of bus devices are bus devices of a similar type.