MEMORY SYSTEM

• US 20160239381A1
• Filed: 09/11/2015
• Published: 08/18/2016
• Est. Priority Date: 02/17/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nakazumi, Shinichiro, Ueki, Katsuhiko, Kojima, Yoshihisa
• Granted Patent: US 9,928,138 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals

Abstract

According to one embodiment, a memory system includes a memory, and a processor. The memory converts an amount of charge held by a memory cell into a value. The processor executes a first process of reading first data from the memory. The processor executes a second process of reading the first data by making the memory use a first determination potential different in a case where error correction of the first data read through the first process is failed. The processor executes a third process of reading second data from the memory by making the memory use a third determination potential in a case where error correction of the first data read through the second process is succeeded. The third determination potential is the first determination potential used by the memory in a case where error correction of the first data read through the second process is succeeded.

Claims

1. A memory system comprising:

a memory configured to be written data therein, the memory including a memory cell configured to hold charge of an amount corresponding to a value included in the data, the memory converting an amount of charge held by the memory cell into the value in reading on the basis of comparison between the amount of charge held by the memory cell and a determination potential;

a first correction unit configured to execute error correction; and

a processor configured to execute a first process of reading first data from the memory, execute a second process of reading the first data by making the memory use a first determination potential different from a second determination potential in a case where the first correction unit fails in error correction of the first data read through the first process, the second determination potential being the determination potential used by the memory in the first process, and execute a third process of reading second data from the memory by making the memory use a third determination potential in a case where the first correction unit succeeds in error correction of the first data read through the second process, the third determination potential being the first determination potential used by the memory in a case where the first correction unit succeeds in error correction of the first data read through the second process.

2. The memory system according to claim 1, wherein in a case where the first correction unit succeeds in error correction of the first data read through the second process, the processor stores setting information indicating the third determination potential therein, and makes the memory use the third determination potential in the third process on the basis of the stored setting information.

3. The memory system according to claim 2, wherein when the first correction unit fails in error correction of the first data read through the second process, the processor changes the first determination potential and executes the second process again.

4. The memory system according to claim 2, wherein the processor has multiple first setting information, and selects second setting information from the multiple first setting information for each second process, the second setting information being setting information indicating the first determination potential.

5. The memory system according to claim 4, wherein the processor has order information, and selects the second setting information from the multiple first setting information in an order according to the order information.

6. The memory system according to claim 4, wherein

the multiple first setting information are associated with identification information, and

the processor has identification information associated with third setting information, and selects the third setting information by referring to the stored identification information, the third setting information being setting information indicating the third determination potential.

7. The memory system according to claim 1, wherein the processor executes refresh of the first data at least on the basis of whether or not the first correction unit fails in error correction of the first data read through the second process.

8. The memory system according to claim 7, wherein the processor executes the first process according to time having elapsed since the first data is written.

9. The memory system according to claim 1, further comprising a second correction unit having a higher correction capability than a correction capability of the first correction unit, the second correction unit executing error correction of the first data read through the second process in a case where the first correction unit fails in error correction of the first data read through the second process.

10. The memory system according to claim 1, wherein the processor has multiple first setting information, selects second setting information from the multiple first setting information for each second process, and converts the selected second setting information into third setting information, the third setting information being information indicating the first determination potential.

11. The memory system according to claim 10, wherein

the memory includes multiple word lines, and

the processor converts the second setting information into the third setting information on the basis of location information of a word line in which the first data is written.

12. The memory system according to claim 11, wherein the memory is a three-dimensional NAND flash memory including the multiple word lines that are stacked.

13. The memory system according to claim 1, wherein

the memory includes multiple storage areas, and

the processor executes management of the determination potentials by a unit of a storage area.

14. The memory system according to claim 13, wherein each of the storage areas is a block, the block being a unit of erase.

15. The memory system according to claim 13, wherein each of the storage areas includes multiple blocks, each block being a unit of erase.

16. The memory system according to claim 15, wherein the processor controls the multiple blocks in parallel.

17. The memory system according to claim 15, wherein

the memory includes first and second chips,

the blocks include a first block included in the first chip and a second block included in the second chip, and

the processor controls the first block and the second block in parallel.

18. The memory system according to claim 13, wherein

the memory includes a word line,

the word line includes two or more memory cells,

each of the memory cells each includes a first bit and a second bit each holding a one-bit value, and

the storage areas include a first storage area constituted by the first bit and a second storage area constituted by the second bit.

19. The memory system according to claim 4, wherein the multiple first setting information are each a difference from a fixed value.

20. A memory system comprising:

a memory configured to be written data therein, the memory being capable of changing a potential used for determination of the data in reading of the data;

a correction unit configured to execute error correction of data read from the memory; and

a processor configured to read the first data from the memory by making the memory use a first potential, read the first data from the memory by making the memory use a second potential, and making the memory use a third potential in reading second data from the memory in a case where error correction of the first data read by using the third potential is successful, the third potential being the first potential or the second potential.