GOA UNIT FOR CO-DRIVING GATE AND COMMON ELECTRODES, DRIVE CIRCUIT AND ARRAY

• US 20160240158A1
• Filed: 02/20/2014
• Published: 08/18/2016
• Est. Priority Date: 01/27/2014
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: XU, Xiangyang
• Granted Patent: US 9,767,750 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0219 Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

The present disclosure discloses a GOA unit for co-driving a gate electrode and a common electrode, including: a trigger; a first selective input circuit; a second selective input circuit which is used to respectively gate the high level input for common electrode and the high level input for gate electrode to the clock end of the trigger in different time sequences to pull up the voltage on the trigger output end; a third selective input circuit which is used to select level signals or edge signals on gate line n+1 and gate line n+4 to serve as the reset signal of the trigger; a fourth selective input circuit which is used to pull down the voltage thereon; a selective output circuit with the input being connected to the trigger output end, for selectively outputting a gate electrode driving signal or a common electrode driving signal.

Claims

1. A GOA unit for co-driving a gate electrode and a common electrode, including:

a trigger, having an input end, a clock end, a reset end, a low level input end and a trigger output end;

a first selective input circuit, including two reverse cutoff diodes connected in parallel, wherein the anodes of the diodes are respectively connected with the outputs of the gate line n−

1 and gate line n+2, and the cathodes of the diodes are used as outputs to be connected with the input end, in order to select level signals or edge signals in the gate line n−

1 and gate line n+2 to serve as the input stimulus signal of the trigger;

a second selective input circuit with an output thereof being connected with the clock end, including four clock pulse inputs having the same cycle but working asynchronously, a high level input for common electrode and a high level input for gate electrode, so as to respectively gate the high level input for common electrode and the high level input for gate electrode to the clock end of the trigger in different time sequences to pull up the voltage on the trigger output end;

a third selective input circuit, including two reverse cutoff diodes connected in parallel, wherein the anodes of the diodes are respectively connected with the outputs of gate line n+1 and gate line n+4, and the cathodes of the diodes are used as outputs to be connected with the reset end, in order to select level signals or edge signals on gate line n+1 and gate line n+4 to serve as the reset signal of the trigger;

a fourth selective input circuit with an output thereof being connected to the low level input end, for respectively gating a gate low level input or a common electrode low level input to the low level input end of the trigger under the control of signals on gate line n+1 and gate line n+4 to pull down the voltage thereon; and

a selective output circuit with an input thereof being connected to the trigger output end, for selectively outputting a gate electrode driving signal or a common electrode driving signal in two of the four clock pulse sequences having the same cycle and working asynchronously.

2. The GOA unit as recited in claim 1, wherein the reverse cutoff diode is a circuit equivalent to a diode composed of an MOS transistor or a TFT transistor, the gate of the MOS transistor or TFT transistor being connected with a source thereof to serve as the anode, and the drain being used as the cathode.

3. The GOA unit as recited in claim 1, wherein the level signals or edge signals in gate line n−

1 and gate line n+2 are low level signals or falling edge signals, and the level signals or edge signals on gate line n+1 and gate line n+4 are high level signals or raising edge signals.

4. The GOA unit as recited in claim 1, wherein the four clock pulse inputs having the same cycle and working asynchronously differ from each other in sequence with ¼

work cycle on phase.

5. The GOA unit as recited in claim 1, wherein the common electrode driving signal output by the GOA unit circuit synchronizes with a signal on gate line n+3.

6. The GOA unit as recited in claim 5, wherein the second selective input circuit includes four TFT transistors,

wherein the sources and drains of two TFT transistors are connected with each other, and two gates are respectively controlled by the second clock pulse input and the third clock pulse input for introducing the high level input for gate electrode;

and the sources and drains of the other two TFT transistors are connected with each other, and the two gates are respectively controlled by the first clock pulse input and the fourth clock pulse input for introducing the high level input for common electrode.

7. The GOA unit as recited in claim 5, wherein the fourth selective input circuit includes two TFT transistors, the gates being respectively connected to the outputs of gate lines n+1 and n+4, and the sources being correspondingly connected with the gate low level input and the common electrode low level input.

8. The GOA unit as recited in claim 5, wherein the selective output circuit includes two TFT transistors, two gates thereof being respectively controlled by the third clock pulse input and the first clock pulse input, and the two sources thereof being connected to the trigger output end together, in order to respectively output the signals of gate line n and common electrode line n+3 in different time sequences, wherein the two pulse sequences have a difference of ¾

work cycle.

9. A circuit for driving display panel, including a plurality of GOA unit as recited in claim 1, wherein the GOA units are cascaded in the following manner:

the outputs of gate lines n−

1 and n+2 are respectively used as the trigger signals of this grade of GOA unit, the outputs of gate lines n+1 and n+4 are respectively used as the reset signals of this grade of GOA unit and four clock lines are respectively connected with the clock pulse inputs on the second selective input circuit of this grade of GOA unit, in order to provide clock signals with the same cycle but in different phases, and the high level input for gate electrode and the high level input for common electrode are respectively introduced under different clock pulses to output corresponding pull-up voltages;

wherein the outputs of this grade of GOA unit include the outputs of gate line n and the common electrode line n+3.

10. The circuit as recited in claim 9, wherein the reverse cutoff diode is a circuit equivalent to a diode composed of an MOS transistor or a TFT transistor, the gate of the MOS transistor or TFT transistor being connected with a source thereof to serve as the anode, and the drain being used as the cathode.

11. The circuit as recited in claim 9, wherein the level signals or edge signals in gate line n−

1 and gate line n+2 are low level signals or falling edge signals, and the level signals or edge signals on gate line n+1 and gate line n+4 are high level signals or raising edge signals.

12. The circuit as recited in claim 9, wherein the four clock pulse inputs having the same cycle and working asynchronously differ from each other in sequence with ¼

work cycle on phase.

13. The circuit as recited in claim 9, wherein, the common electrode driving signal output by the GOA unit circuit synchronizes with a signal on gate line n+3.

14. The circuit as recited in claim 13, wherein the second selective input circuit includes four TFT transistors, wherein the sources and drains of two TFT transistors are connected with each other, and two gates are respectively controlled by the second clock pulse input and the third clock pulse input, for introducing the high level input for gate electrode;

and

the sources and drains of the other two TFT transistors are connected with each other, and the two gates are respectively controlled by the first clock pulse input and the fourth clock pulse input for introducing the high level input for common electrode.

15. The circuit as recited in claim 13, wherein, the fourth selective input circuit includes two TFT transistors, the gates being respectively connected to the outputs of gate lines n+1 and n+4, and the sources being correspondingly connected with the gate low level input and the common electrode low level input.

16. The circuit as recited in claim 13, wherein, the selective output circuit includes two TFT transistors, two gates thereof being respectively controlled by the third clock pulse input and the first clock pulse input, and the two sources thereof being connected to the trigger output end together, in order to respectively output the signals of gate line n and common electrode line n+3 in different time sequences, wherein the two pulse sequences have a difference of ¾

work cycle.

17. An array with the circuit as recited in claim 9 placed thereon, including:

a gate line and a common electrode line, which are arranged in parallel along a transverse direction; and

a clock input line, a gate high and low level input line and common electrode high and low level input lines, which are arranged in parallel along a longitudinal direction,

wherein the corresponding outputs of the gate line and the common electrode line have a difference of 3 grades in terms of cascade positions, or ¾

work cycle on time sequence.