Clock Switching in Always-On Component
First Claim
1. A method comprising:
- monitoring audio samples in a first component in an integrated circuit during a time that a remainder of the integrated circuit is powered down, wherein the first component is powered on during the time and is operating according to a first clock;
detecting a key phrase in the audio samples by the first component;
powering up a memory controller and initializing the memory controller to store the audio samples in a memory;
powering up at least a portion of the integrated circuit including the memory controller responsive to the detecting;
determining that a second clock used within the integrated circuit is available, wherein the second clock has at least one characteristic that is closer to an ideal clock for the integrated circuit than a corresponding characteristic of the first clock, and wherein the second clock becomes available responsive to powering up the portion of the integrated circuit; and
switching to the second clock in the first component at a time that is not near an arrival of subsequent audio samples to ensure no more than a threshold number of audio samples is lost or corrupted during the switching.
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Accused Products
Abstract
In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.
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Citations
20 Claims
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1. A method comprising:
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monitoring audio samples in a first component in an integrated circuit during a time that a remainder of the integrated circuit is powered down, wherein the first component is powered on during the time and is operating according to a first clock; detecting a key phrase in the audio samples by the first component; powering up a memory controller and initializing the memory controller to store the audio samples in a memory; powering up at least a portion of the integrated circuit including the memory controller responsive to the detecting; determining that a second clock used within the integrated circuit is available, wherein the second clock has at least one characteristic that is closer to an ideal clock for the integrated circuit than a corresponding characteristic of the first clock, and wherein the second clock becomes available responsive to powering up the portion of the integrated circuit; and switching to the second clock in the first component at a time that is not near an arrival of subsequent audio samples to ensure no more than a threshold number of audio samples is lost or corrupted during the switching. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 13)
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11. An integrated circuit comprising:
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one or more processors; a memory controller and a memory; and a first circuit coupled to the one or more processors and the memory controller, wherein the first circuit is configured to; remain powered up during times that the one or more processors are powered down; receive a first plurality of audio samples captured by one or more audio input devices during a time that the one or more processors are powered down, wherein the first circuit operates according to a first clock during the time that the one or more processors are powered down; detect a predetermined pattern in the first plurality of audio samples; cause the memory controller to power up and initialize the memory controller to store the first plurality of audio samples in a memory responsive to detecting the predetermined pattern; cause the one or more processors to power up responsive to detecting the predetermined pattern, wherein a second clock activates responsive to the power up; and switch to the second clock responsive to the second clock becoming operable at a time that is not near an arrival of a subsequent second plurality of audio samples. - View Dependent Claims (12, 14, 15, 16, 17, 18)
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19. A system comprising:
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an audio input device; an audio coder/decoder (codec) coupled to the audio input device and configured to generate audio samples from sound detected by the audio input device; a memory; and an integrated circuit coupled to the audio codec and the memory, wherein the integrated circuit includes an audio filter circuit, one or more processors, and a memory controller coupled to the memory, and wherein; the audio filter circuit is configured to detect a predetermined pattern in the audio samples from the audio codec during a time that a memory controller and the one or more processors are powered down, wherein the audio filter circuit operates according to a first clock during the time; the audio filter circuit is configured to cause the memory controller and the processors to power up responsive to detecting the predetermined pattern, wherein the power up causes a second clock to activate in the integrated circuit; and the audio filter circuit configured to switch from the first clock to the second clock responsive to activation of the second clock at a time that is not near an arrival of subsequent audio samples. - View Dependent Claims (20)
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Specification