MEMORY PROGRAMMING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE

• US 20160240256A1
• Filed: 04/22/2015
• Published: 08/18/2016
• Est. Priority Date: 02/16/2015
• Status: Active Grant

• Current Assignee: Phison Electronics Corporation
• Original Assignee: Phison Electronics Corporation
• Inventors: Lin, Wei, Hsu, Yu-Cheng, Liu, An-Cheng, Lam, Siu-Tung
• Granted Patent: US 9,496,041 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A memory programming method for a rewritable non-volatile memory module having memory cells is provided. The memory programming method includes: performing a first programming process on the memory cells according to write data and obtaining a first programming result of the first programming process; grouping the memory cells into programming groups according to the first programming result; and performing a second programming process on the memory cells according to the write data. The second programming process includes: programming a first programming group among the programming groups by using a first program voltage; and programming a second programming group among the programming groups by using a second program voltage. The first program voltage and the second program voltage are different. Moreover, a memory control circuit unit and a memory storage device are provided.

Claims

1. A memory programming method for a rewritable non-volatile memory module having a plurality of memory cells, the memory programming method comprising:

performing a first programming process on the memory cells according to write data and obtaining a first programming result of the first programming process;

grouping the memory cells into a plurality of programming groups according to the first programming result; and

performing a second programming process on the memory cells according to the write data,

wherein the second programming process comprises;

programming a first programming group among the programming groups by using a first program voltage; and

programming a second programming group among the programming groups by using a second program voltage, wherein the first program voltage and the second program voltage are different.

2. The memory programming method according to claim 1, wherein a first voltage distribution range of the first programming group and a second voltage distribution range of the second programming group are different.

3. The memory programming method according to claim 2, wherein a first voltage of a first memory cell in the first programming group is smaller than a second voltage of a second memory cell in the second programming group,

wherein the first program voltage is greater than the second program voltage.

4. The memory programming method according to claim 1, wherein the step of grouping the memory cells into the programming groups according to the first programming result comprises:

providing at least one grouping voltage to the memory cells to obtain storage state information of the memory cells, wherein the storage state information indicates a voltage distribution status of the memory cells; and

grouping the memory cells into the programming groups according to the storage state information.

5. The memory programming method according to claim 1, further comprising:

determining whether the first programming result meets a predetermined programming result corresponding to the write data,

wherein the step of grouping the memory cells into the programming groups according to the first programming result is performed after determining that the first programming result does not meet the predetermined programming result.

6. The memory programming method according to claim 5, wherein the step of determining whether the first programming result meets the predetermined programming result comprises:

providing a verification voltage to the memory cells to determine whether a storage state of the memory cells is in an accurate storage state corresponding to the write data;

if the storage state of the memory cells is in the accurate storage state corresponding to the write data, determining that the first programming result meets the predetermined programming result; and

if the storage state of the memory cells is not in the accurate storage state corresponding to the write data, determining that the first programming result does not meet the predetermined programming result.

7. The memory programming method according to claim 1, further comprising:

grouping the memory cells into a third programming group and a fourth programming group before performing the first programming process.

8. The memory programming method according to claim 7, wherein a third voltage of a third memory cell in the third programming group is smaller than a fourth voltage of a fourth memory cell in the fourth programming group,

wherein the first programming process comprises:

programming the third programming group by using a third program voltage; and

programming the fourth programming group by using a fourth program voltage,

wherein the third program voltage is greater than the fourth program voltage, the first program voltage is greater than the third program voltage, and the second program voltage is greater than the fourth program voltage.

9. A memory storage device, comprising:

a connection interface unit configured to couple to a host system;

a rewritable non-volatile memory module comprising a plurality of memory cells; and

a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module,

wherein the memory control circuit unit is configured to transmit a first write command sequence configured to instruct to perform a first programming process on the memory cells according to write data,

wherein the memory control circuit unit is further configured to obtain a first programming result of the first programming process,

wherein the memory control circuit unit is further configured to group the memory cells into a plurality of programming groups according to the first programming result,

wherein the memory control circuit unit is further configured to transmit a second write command sequence configured to instruct to perform a second programming process on the memory cells according to the write data,

wherein the second programming process comprises;

programming a first programming group among the programming groups by using a first program voltage; and

programming a second programming group among the programming groups by using a second program voltage, wherein the first program voltage and the second program voltage are different.

10. The memory storage device according to claim 9, wherein a first voltage distribution range of the first programming group and a second voltage distribution range of the second programming group are different.

11. The memory storage device according to claim 10, wherein a first voltage of a first memory cell in the first programming group is smaller than a second voltage of a second memory cell in the second programming group,

wherein the first program voltage is greater than the second program voltage.

12. The memory storage device according to claim 9, wherein the operation of the memory control circuit unit grouping the memory cells into the programming groups according to the first programming result comprise:

transmitting a grouping instruction configured to instruct to provide at least one grouping voltage to the memory cells to obtain storage state information of the memory cells, wherein the storage state information indicates a voltage distribution status of the memory cells; and

grouping the memory cells into the programming groups according to the storage state information.

13. The memory storage device according to claim 9, wherein the memory control circuit unit is further configured to determine whether the first programming result meets a predetermined programming result corresponding to the write data,

wherein the operation of the memory control circuit unit grouping the memory cells into the programming groups according to the first programming result is performed after determining that the first programming result does not meet the predetermined programming result.

14. The memory storage device according to claim 13, wherein the operation of the memory control circuit unit determining whether the first programming result meets the predetermined programming result corresponding to the write data comprises:

transmitting a verification instruction configured to instruct to provide a verification voltage to the memory cells to determine whether a storage state of the memory cells is in an accurate storage state corresponding to the write data;

if the storage state of the memory cells is in the accurate storage state corresponding to the write data, determining that the first programming result meets the predetermined programming result; and

if the storage state of the memory cells is not in the accurate storage state corresponding to the write data, determining that the first programming result does not meet the predetermined programming result.

15. The memory storage device according to claim 9, wherein the memory control circuit unit is further configured to group the memory cells into a third programming group and a fourth programming group before the first programming process is performed.

16. The memory storage device according to claim 15, wherein a third voltage of a third memory cell in the third programming group is smaller than a fourth voltage of a fourth memory cell in the fourth programming group,

wherein the first programming process comprises:

programming the third programming group by using a third program voltage; and

programming the fourth programming group by using a fourth program voltage,

wherein the third program voltage is greater than the fourth program voltage, the first program voltage is greater than the third program voltage, and the second program voltage is greater than the fourth program voltage.

17. A memory control circuit unit configured to control a rewritable non-volatile memory module having a plurality of memory cells, the memory control circuit unit comprising:

a host interface configured to couple to a host system;

a memory interface configured to couple to the rewritable non-volatile memory module; and

a memory management circuit coupled to the host interface and the memory interface,

wherein the memory management circuit is configured to transmit a first write command sequence configured to instruct to perform a first programming process on the memory cells according to write data,

wherein the memory management circuit is further configured to obtain a first programming result of the first programming process,

wherein the memory management circuit is further configured to group the memory cells into a plurality of programming groups according to the first programming result,

wherein the memory management circuit is further configured to transmit a second write command sequence configured to instruct to perform a second programming process on the memory cells according to the write data,

wherein the second programming process comprises;

programming a first programming group among the programming groups by using a first program voltage; and

programming a second programming group among the programming groups by using a second program voltage, wherein the first program voltage and the second program voltage are different.

18. The memory control circuit unit according to claim 17, wherein a first voltage distribution range of the first programming group and a second voltage distribution range of the second programming group are different.

19. The memory control circuit unit according to claim 18, wherein a first voltage of a first memory cell in the first programming group is smaller than a second voltage of a second memory cell in the second programming group,

wherein the first program voltage is greater than the second program voltage.

20. The memory control circuit unit according to claim 17, wherein the operation of the memory management circuit grouping the memory cells into the programming groups according to the first programming result comprises:

transmitting a grouping instruction configured to instruct to provide at least one grouping voltage to the memory cells to obtain storage state information of the memory cells, wherein the storage state information indicates a voltage distribution status of the memory cells; and

grouping the memory cells into the programming groups according to the storage state information.

21. The memory control circuit unit according to claim 17, wherein the memory management circuit is further configured to determine whether first programming result meets a predetermined programming result corresponding to the write data,

wherein the operation of the memory management circuit grouping the memory cells into the first programming group according to the first programming result is performed after determining that the first programming result does not meet the predetermined programming result.

22. The memory control circuit unit according to claim 21, wherein the operation of the memory management circuit determining whether the first programming result meets the predetermined programming result corresponding to the write data comprises:

transmitting a verification instruction configured to instruct to provide a verification voltage to the memory cells to determine whether a storage state of the memory cells is in an accurate storage state corresponding to the write data;

if the storage state of the memory cells is the accurate storage state corresponding to the write data, determining that the first programming result meets the predetermined programming result; and

if the storage state of the memory cells is not in the accurate storage state corresponding to the write data, determining that the first programming result does not meet the predetermined programming result.

23. The memory control circuit unit according to claim 17, wherein the memory management circuit is further configured to group the memory cells into a third programming group and a fourth programming group before the first programming process is performed.

24. The memory control circuit unit according to claim 23, wherein a third voltage of a third memory cell in the third programming group is smaller than a fourth voltage of a fourth memory cell in the fourth programming group,

wherein the first programming process comprises:

programming the third programming group by using a third program voltage; and

programming the fourth programming group by using a fourth program voltage,

wherein the third program voltage is greater than the fourth program voltage, the first program voltage is greater than the third program voltage, and the second program voltage is greater than the fourth program voltage.