VERTICAL CMOS STRUCTURE AND METHOD

• US 20160240533A1
• Filed: 03/06/2015
• Published: 08/18/2016
• Est. Priority Date: 02/13/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Oxland, Richard Kenneth
• Granted Patent: US 9,472,551 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02636 Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/068 : comprising a junction
• CPC Class Codes: H01L 29/1037 : and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/16 : including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/20 : including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/26 : including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24 , e.g. alloys
• CPC Class Codes: H01L 29/267 : in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/42376 : characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/42392 : fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66469 : with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
• CPC Class Codes: H01L 29/66666 : Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66742 : Thin film unipolar transistors
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78642 : Vertical transistors
• CPC Class Codes: H01L 29/78681 : having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 : having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method for forming stacked, complementary transistors is disclosed. Selective deposition techniques are used to form a column having a lower portion that includes one type of semiconductor (e.g. germanium) and an upper portion of another type of semiconductor (e.g. indium arsenide. The lower portion of the column provides a channel region for a transistor of one type, while the upper column provides a channel region for a transistor of another type. This provides a complementary pair that occupies a minimum of integrated circuit surface area. The complementary transistors can be utilized in a variety of circuit configurations. Described are complementary transistors where the lower transistor is p-type and the upper transistor is n-type.

Claims

1. A complementary transistor structure comprising:

a lower portion of a column comprising a second semiconductive material formed on a substrate comprising a first semiconductor material;

a first gate surrounding and insulated from the lower portion of the column;

an upper portion of the column comprising a third semiconductive material;

a second gate surrounding and insulated from the lower portion of the column;

a first electrical contact to the upper portion of the column above the second gate; and

a second electrical contact to the upper portion and lower portion of the column between the first and second gates.

7. The complementary transistor structure as in claim 1 wherein the second semiconductive material is germanium.

8. The complementary transistor structure as in claim 1 wherein the third semiconductive material is indium arsenide.

21. The complementary transistor structure as in claim 1 wherein the second semiconductive material contacts the third semiconductive material.

22. The complementary transistor structure as in claim 1 wherein the second semiconductive material is separated from the third semiconductive material.

23. The complementary transistor structure as in claim 1 wherein the second semiconductive material and the third semiconductive material are opposite conductivity types.

24. The complementary transistor structure as in claim 1 wherein the first gate is electrically coupled to the second gate.

25. The complementary transistor structure as in claim 1 wherein the substrate immediately below the lower portion is electrically coupled to ground.

2-6. -6. (canceled)

9. A complementary transistor structure comprising:

a lower portion of a column comprising crystalline germanium formed on a silicon substrate;

a first gate surrounding and insulated from the lower portion of the column;

an upper portion of the column formed on top of the lower portion of the column comprising indium arsenide;

a second gate surrounding and insulated from the lower portion of the column;

a first electrical contact to the upper portion of the column above the second gate; and

a second electrical contact to the upper portion and lower portion of the column between the first and second gates.

10. The complementary transistor structure as in claim 9 wherein the lower portion of the column provides a channel region for a p-type field effect transistor and the upper portion of the column provides a channel region for an n-type field effect transistor.

11. The complementary transistor structure as in claim 9 wherein the lower portion of the column provides a channel region for an n-type field effect transistor and the upper portion of the column provides a channel region for an p-type field effect transistor.

12. The complementary transistor structure as in claim 9 wherein the first gate is insulated from the lower portion of the column by a high-k dielectric.

13. The complementary transistor structure as in claim 9 wherein the second gate is insulated from the upper portion of the column by a high-k dielectric.

14-20. -20. (canceled)

26. A complementary transistor structure comprising:

a first vertical nanowire extending from a substrate, the first vertical nanowire being a first semiconductor material;

a second vertical nanowire extending from the first vertical nanowire, the first vertical nanowire being disposed between the second vertical nanowire and the substrate, the second vertical nanowire being a second semiconductor material different than the first semiconductor material;

a first gate adjacent a first channel region of the first vertical nanowire; and

a second gate adjacent a second channel region of the second vertical nanowire, a common source/drain region being interposed between the first gate and the second gate.

27. The complementary transistor structure of claim 26, further comprising a gate contact electrically coupled to the first gate and the second gate.

28. The complementary transistor structure of claim 26, further comprising an electrical contact electrically coupled to the common source/drain region.

29. The complementary transistor structure of claim 28, wherein the electrical contact contacts the second vertical nanowire.

30. The complementary transistor structure of claim 26, wherein the first gate and the first vertical nanowire form a first transistor of a first conductivity type, the second gate and the second vertical nanowire form a second transistor of a second conductivity type, the first conductivity type being different than the second conductivity type.

31. The complementary transistor structure of claim 26, wherein the first semiconductor material directly contacts the second semiconductor material.

32. The complementary transistor structure of claim 26, further comprising a high-k dielectric material interposed between the first gate and the first vertical nanowire and interposed between the second gate and the second vertical nanowire.