BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 4/15 AND 1024-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME
First Claim
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1. A bit interleaver, comprising:
- a first memory configured to store a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15;
a processor configured to generate an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; and
a second memory configured to provide the interleaved codeword to a modulator for 1024-symbol mapping.
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Abstract
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.
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Citations
6 Claims
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1. A bit interleaver, comprising:
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a first memory configured to store a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15; a processor configured to generate an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; and a second memory configured to provide the interleaved codeword to a modulator for 1024-symbol mapping. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification