BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 2/15 AND 4096-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

• US 20160241266A1
• Filed: 03/27/2015
• Published: 08/18/2016
• Est. Priority Date: 02/16/2015
• Status: Active Grant

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: PARK, Sung-Ik, KWON, Sun-Hyoung, LEE, Jae-Young, KIM, Heung-Mook, HUR, Nam-Ho
• Granted Patent: US 10,447,306 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03M 13/1165 QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
• CPC Class Codes: H03M 13/255 with Low Density Parity Check [LDPC] codes
• CPC Class Codes: H03M 13/271 Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
• CPC Class Codes: H03M 13/2778 Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices

Abstract

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.

Claims

1. A bit interleaver, comprising:

a first memory configured to store a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15;

a processor configured to generate an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; and

a second memory configured to provide the interleaved codeword to a modulator for 4096-symbol mapping.

2. The bit interleaver of claim 1, wherein the 4096-symbol mapping is a Non-Uniform Constellation (NUC) symbol mapping which corresponds to 4096 constellations.

3. The bit interleaver of claim 2, wherein the parallel factor is 360, and the bit group includes 360 bits.

4. The bit interleaver of claim 3, wherein the LDPC codeword is represented by (u₀, u₁, . . . , u_Nldpc−

1) (where N_ldpc is

     64800), and is divided into 180 bit groups each including 360 bits, as in the following equation;

X_j={u_k|360×

j≦

k<

360×

(j+1), 0≦

k<

N_ldpc} for 0≦

j<

N_group

where X_j is an j-th bit group, N_ldpc is 64800, and N_group is 180.

5. The bit interleaver of claim 4, wherein the interleaving is performed using the following equation using permutation order:

Y_j=X<sub>π

(j)</sub> 0≦

j≦

N_group

where X_j is the j-th bit group, Y_j is an interleaved j-th bit group, and π

(j) is a permutation order for bit group-based interleaving.

6. The bit interleaver of claim 5, wherein the permutation order corresponds to an interleaving sequence represented by the following equation:

interleaving sequence={14 129 71 96 171 36 144 64 162 4 86 128 113 7 105 131 2 133 106 79 11 152 26 118 158 126 17 55 45 111 138 84 6 52 167 38 20 101 31 120 5 112 74 69 121 9 154 15 146 116 63 1 114 83 124 109 39 75 123 57 49 30 21 40 43 77 157 44 13 99 34 147 166 56 155 176 95 102 119 161 37 159 97 68 122 163 89 61 107 22 10 127 87 103 179 172 66 59 8 145 88 132 110 54 47 153 25 32 73 42 148 150 28 91 18 24 19 53 136 48 76 35 151 173 149 142 160 94 117 169 165 141 80 67 170 164 82 65 60 135 168 23 100 134 90 98 125 85 137 81 41 156 50 3 29 16 72 177 0 78 62 139 93 46 12 175 130 51 178 92 115 174 27 70 58 33 104 140 108 143}