TIME TO DIGITAL CONVERTER AND PHASE LOCKED LOOP

• US 20160241301A1
• Filed: 02/11/2016
• Published: 08/18/2016
• Est. Priority Date: 02/17/2015
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: PAVLOVIC, NENAD, DYACHENKO, Vladislav, SARIC, Tarik
• Granted Patent: US 9,584,177 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03C 3/0925 applying frequency modulation at the divider in the feedback loop
• CPC Class Codes: H03C 3/0933 using fractional frequency division in the feedback loop of the phase locked loop
• CPC Class Codes: H03C 3/0941 applying frequency modulation at more than one point in the loop
• CPC Class Codes: H03C 3/095 applying frequency modulation to the loop in front of the voltage controlled oscillator
• CPC Class Codes: H03C 3/0958 applying frequency modulation by varying the characteristics of the voltage controlled oscillator
• CPC Class Codes: H03C 3/0991 including calibration means or calibration methods
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H04B 1/7073 Synchronisation aspects
• CPC Class Codes: H04B 2001/6912 using chirp
• CPC Class Codes: H04B 2201/7073 Direct sequence modulation synchronisation

Abstract

A phase locked loop is disclosed having a frequency controlled oscillator (42), a feedback path, a time to digital converter (10) and a memory. The frequency controlled oscillator (42) comprises a first control input (135, 136) for varying the frequency of the output (106) of the frequency controlled oscillator (42) so as to track a reference frequency (101) and a second control input (139) for modulating the frequency of the output signal (106) so as to produce a chirp. The feedback path is configured to provide an input signal (107) to the time to digital converter (10), and comprises modulation cancelling module (14) operable to remove the frequency modulation resulting from the second control input (139) from the output signal (106). The memory stores second control input values that each correspond with a desired chirp frequency and which compensate for non-linearity in the response of the frequency controlled oscillator to the second control input (139). The phase locked loop is operable in a chirp mode, in which the second control input (139) is produced by determining a value for the second control input (139) corresponding with a desired chirp frequency based on the stored second control input values in the memory, and in which the phase locked loop is configured to determine the first control input (135, 136) based on the feedback path from which the modulation cancelling module (14) has removed the frequency modulation resulting from the second control input (139).

Claims

1. A phase locked loop having a frequency controlled oscillator, a feedback path, a time to digital converter, and a memory, wherein:

the frequency controlled oscillator comprises a first control input for varying a frequency of an output signal of the frequency controlled oscillator so as to track a reference frequency and a second control input for modulating the frequency of the output signal so as to produce a chirp;

the feedback path is configured to provide an input signal based on the output signal of the frequency controlled oscillator to the time to digital converter, and comprises a modulation cancelling module operable to remove the frequency modulation resulting from the second control input from the output signal;

the memory stores second control input values that each correspond with a desired chirp frequency and which compensate for non-linearity in a response of the frequency controlled oscillator to the second control input; and

wherein the phase locked loop is operable in a chirp mode, in which the second control input is produced by determining a value for the second control input corresponding with a desired chirp frequency based on the stored second control input values in the memory, and in which the phase locked loop is configured to determine the first control input based on the feedback path from which the modulation cancelling module has removed the frequency modulation resulting from the second control input.

2. The phase locked loop of claim 1, wherein the phase locked loop comprises a frequency divider that receives the output signal and outputs the input signal to the time to digital converter;

and a control block that controls the operation of the frequency divider, wherein the control block comprises a sigma-delta modulator for fractional-n frequency control.

3. The phase locked loop of claim 2, further comprising a quantisation noise cancelling module, configured to receive a signal based on the output of the time to digital converter and to reduce quantisation noise arising from quantisation in the control block.

4. The phase locked loop of claim 2, wherein the modulation cancelling module comprises the frequency divider.

5. The phase locked loop of claim 1, wherein the second control input comprises an analog input.

6. The phase locked loop of claim 1, wherein the first control input comprises a digital control input.

7. The phase locked loop of claim 1, wherein the frequency controlled oscillator comprises a switched capacitor varactor responsive to the first control input, and an analog varactor responsive to the second control input.

8. The phase locked loop of claim 7, wherein the first control input comprises a tracking input and an acquisition input, corresponding with a tracking switched capacitor bank and an acquisition switched capacitor bank, wherein the acquisition bank is operable to produce a larger tuning range of the frequency controlled oscillator than the tracking bank.

9. The phase locked loop of claim 8, wherein during chirp mode, the acquisition tuning bank is operable to maintain lock when the range of the tuning bank has been exceeded.

10. The phase locked loop of claim 9, further comprising a digital to analog converter, configured to convert the stored second control input values from the memory to an analog signal.

11. The phase locked loop of claim 10, further comprising a low pass filter between the output of the digital to analog converter and the second control input.

12. The phase locked loop of claim 1, wherein:

the phase locked loop further comprises a loop filter that receives a phase error signal based on the output of the time to digital converter and is configured to provide the first control signal to the frequency controlled oscillator; and

the phase locked loop is operable in a calibration mode, in which;

the modulation cancelling module does not remove the frequency modulation resulting from the second control input in the feedback path, and

the second control input is based on an output of the loop filter.

13. The phase locked loop of claim 12, wherein the phase locked loop is operable in the calibration mode to determine each of the stored second control input values by successively locking the phase locked loop onto each frequency of the chirp using the second control input, and storing in the memory a value based on the second control input after each lock has been achieved.

14. The phase locked loop of claim 1, wherein the time to digital converter comprises:

a synchronisation block configured to output a voltage pulse with duration based on a time difference between a reference oscillating signal and an input oscillating signal;

a charge pump arranged to receive the voltage pulse and to convert the voltage pulse into a current pulse;

an integrator comprising an integrator capacitor, the integrator being configured to receive the current pulse and integrate the current pulse as a charge on the integrator capacitor, resulting in an integrator output voltage; and

a successive approximation register configured to determine the integrator output voltage with respect to a reference voltage by adjusting the charge on the integrator capacitor so as to reduce the integrator output voltage to within a least significant bit of a reference voltage by successive approximation, and configured to output the determined integrator output voltage as a digital signal.

15. A proximity radar comprising the phase locked loop of claim 1.