TIMING ADVANCE ENHANCEMENTS FOR CELLULAR COMMUNICATIONS

• US 20160242133A1
• Filed: 04/22/2016
• Published: 08/18/2016
• Est. Priority Date: 03/12/2010
• Status: Active Grant

• Current Assignee: Malikie Innovations Limited (Key Patent Innovations Limited)
• Original Assignee: Blackberry Limited
• Inventors: FAURIE, Rene, VENKOB, Satish, HOLE, David Philip, Borsella, Remo, Kreuzer, Werner Karl, HANOV, Steven Michael
• Granted Patent: US 9,807,715 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H04W 56/0005 synchronizing of arrival of multiple uplinks
• CPC Class Codes: H04W 56/0045 compensating for timing error by altering transmission time
• CPC Class Codes: H04W 74/0833 Random access procedures, e.g. with 4-step access
• CPC Class Codes: H04W 74/0866 using a dedicated channel for access

Abstract

A disclosed example method involves, when a device is operating in a stationary mode and before a need of the device to communicate data, determining whether a stored timing advance is valid. When the stored timing advance is not valid, a valid timing advance is determined before the need of the device to communicate the data.

Claims

1. A method comprising:

when a device is operating in a stationary mode and before a need of the device to communicate data, determining whether a stored timing advance is valid; and

when the stored timing advance is not valid, determining a valid timing advance before the need of the device to communicate the data.

2. A method as defined in claim 1, further comprising, when the stored timing advance is valid, maintaining the device in the stationary mode without communicating the data.

3. A method as defined in claim 1, wherein determining the valid timing advance comprises transmitting an access burst over a random access channel (RACH).

4. A method as defined in claim 1, wherein determining whether the stored timing advance is valid comprises determining whether a pre-determined number of attempts to access a network have failed when the device is in the stationary mode.

5. A method as defined in claim 1, wherein determining whether the stored timing advance is valid comprises determining whether the device has moved.

6. A method as defined in claim 1 further comprising:

after determining the valid timing advance, using the valid timing advance for a subsequent data transfer.

7. An apparatus comprising:

a processor configured to;

when a device is operating in a stationary mode and before a need of the device to communicate data, determine whether a stored timing advance is valid; and

when the stored timing advance is not valid, determine a valid timing advance before the need of the device to communicate the data.

8. An apparatus as defined in claim 7, wherein the processor is further configured to, when the stored timing advance is valid, cause the device to remain in the stationary mode without communicating the data.

9. An apparatus as defined in claim 7, wherein the processor is to determine the valid timing advance by causing the device to transmit an access burst over a random access channel (RACH).

10. An apparatus as defined in claim 7, wherein the processor is configured to determine whether the stored timing advance is valid by determining whether a pre-determined number of attempts to access a network have failed when the device is in the stationary mode.

11. An apparatus as defined in claim 7, wherein the processor is configured to determine whether the stored timing advance is valid by determining whether the device has moved.

12. An apparatus as defined in claim 7 further comprising:

after determining the valid timing advance, using the valid timing advance for a subsequent data transfer.

13. A computer readable storage memory having instructions stored thereon that, when executed, cause a machine to at least:

when a device is operating in a stationary mode and before a need of the device to communicate data, determine whether a stored timing advance is valid; and

when the stored timing advance is not valid, determine a valid timing advance before the need of the device to communicate the data.

14. A computer readable storage memory as defined in claim 13, wherein the instructions further cause the machine to, when the stored timing advance is valid, cause the device to remain in the stationary mode without communicating the data.

15. A computer readable storage memory as defined in claim 13, wherein the instructions further cause the machine to determine the valid timing advance by transmitting an access burst over a random access channel (RACH).

16. A computer readable storage memory as defined in claim 13, wherein the instructions further cause the machine to determine whether the stored timing advance is valid by determining whether a pre-determined number of attempts to access a network have failed when the device is in the stationary mode.

17. A computer readable storage memory as defined in claim 13, wherein the instructions further cause the machine to determine whether the stored timing advance is valid by determining whether the device has moved.

18. A computer readable storage memory as defined in claim 13 further comprising:

after determining the valid timing advance, using the valid timing advance for a subsequent data transfer.