Compute Through Power Loss Approach For Processing Device Having Nonvolatile Logic Memory

• US 20160246355A1
• Filed: 10/20/2015
• Published: 08/25/2016
• Est. Priority Date: 02/25/2015
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments Deutschland Gesellschaft Mit Beschrã¤Nkter Haftung (Texas Instruments, Inc.), Texas Instruments, Inc.
• Inventors: Dannenberg, Andreas, Peterson, Brent, Goh, Aik K., Zwerg, Michael, Schreiner, Joerg, Bartling, Steven Craig
• Granted Patent: US 10,037,071 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A computing device apparatus facilitates use of a deep low power mode that includes powering off the device'"'"'s CPU by including a software routine configured to be run by the CPU that effects saving to a non-volatile memory a state of the CPU and/or the device'"'"'s peripherals before entering the deep low-power mode. The software routine can be configured to control this state storage in response to detecting a low power event, i.e., loss of power sufficient to run the CPU, or a software command to enter the deep low power mode to save power as part of an efficiency program. Then, upon wake up from the deep low power mode, the software routine is first run by the CPU to effect restoring from the non-volatile memory the state of the CPU and the peripherals before execution of a primary application for the central processing unit.

Claims

1. A computing device apparatus comprising:

a central processing unit;

a memory sub-system;

a non-volatile memory;

a power management unit or peripheral power sensing device configured to detect presence or absence of power for the central processing unit;

wherein the power management unit is configured to effect switching off power applied to the central processing unit, peripherals for the computing device apparatus, and the memory sub-system to reach a deep low-power mode;

a software routine configured to be run by the central processing unit to effect saving to the non-volatile memory a state of the central processing unit and the peripherals before entering the deep low-power mode and to effect restoring the state of the central processing unit and the peripherals from the non-volatile memory before execution of a primary application for the central processing unit;

wherein the software routine is configured to be triggered to effect saving the state and entry into the deep low power mode in response to one or more of receiving indication of a power loss from the power management unit or the peripheral power sensing device, a software request to enter the deep low power mode, or a peripheral driven interrupt event.

2. The computing device apparatus of claim 1 wherein the non-volatile memory comprises one or more of FLASH, FRAM, MRAM, or RRAM.

3. The computing device apparatus of claim 1 wherein the software routine is configured to store the state of the central processing unit by storing one or more of program counters, stack pointers, status registers, general purpose registers, or other key state information of the central processing unit.

4. The computing device apparatus of claim 1 wherein the software routine is configured to store the state of the one or more peripherals associated with the central processing unit by storing one or more of peripheral configuration registers, peripheral state registers, peripheral status registers, peripheral data buffers, and other key peripheral state information.

5. The computing device apparatus of claim 1 wherein the non-volatile memory has a write cycle endurance of or greater than 10¹⁴.

6. A method comprising:

operating a processing device having a central processing unit and using a plurality of volatile storage elements;

detecting a deep sleep event including one or both of a low power event for the processing device or a software signal to enter a deep low power mode, which includes powering off the central processing unit;

in response to detecting the deep sleep event and before allowing entry into a deep low power mode by the central processing unit, using a software routine operating on the central processing unit to effect storage of a state comprising contents of the plurality of volatile storage elements of the central processing unit and/or one or more peripherals for the central processing unit to non-volatile memory;

detecting while in the deep low power mode a wake up event including one or both of restoration of power to the processing device or a software signal to wake up;

in response to detecting the wake up event, using the software routine to effect restoring at least a portion of the state from the non-volatile memory in lieu of execution of a wake up process for the central processing unit from the deep low power mode.

7. The method of claim 6 wherein the effecting storage of the state comprises effecting storing of the state in one or more of FLASH, FRAM, MRAM, or RRAM.

8. The method of claim 6 wherein the effecting storage of the state comprises storing program counters, stack pointers, status registers, general purpose registers, and other key state information of the central processing unit.

9. The method of claim 6 wherein the effecting storage of the state comprises storing peripheral configuration registers, peripheral state registers, peripheral status registers, peripheral data buffers, and other key peripheral state information.

10. A computing device apparatus comprising:

a central processing unit;

a memory sub-system;

a non-volatile memory comprising one or more of FLASH, FRAM, MRAM, or RRAM;

a power management unit or peripheral power sensing device configured to detect presence or absence of power for the central processing unit;

wherein the power management unit is configured to effect switching off power applied to the central processing unit, peripherals for the computing device apparatus, and the memory sub-system to reach a deep low-power mode;

a software routine configured to be run by the central processing unit to effect saving to the non-volatile memory a state of the central processing unit and the peripherals before entering the deep low-power mode and to effect restoring the state of the central processing unit and the peripherals from the non-volatile memory before execution of a primary application for the central processing unit;

wherein the non-volatile memory software routine is configured to store the state of the central processing unit by storing one or more of program counters, stack pointers, status registers, general purpose registers, or other key state information of the central processing unit;

wherein the non-volatile memory software routine is configured to store the state of the one or more peripherals associated with the central processing unit by storing one or more of peripheral configuration registers, peripheral state registers, peripheral status registers, peripheral data buffers, and other key peripheral state information;

wherein the software routine is configured to be triggered to save the state and enter the deep low power mode in response to one or more of receiving indication of a power loss from the power management unit or the peripheral power sensing device, a software request to enter the deep low power mode, or a peripheral driven interrupt event;

wherein, in response to detecting sufficient power to exit a low power mode or recover from a power loss condition, the power management unit is configured to issue a power up signal regarding exiting a deep low power mode or power loss condition.