EFFICIENT MAPPING SCHEME WITH DETERMINISTIC POWER TRANSITION TIMES FOR FLASH STORAGE DEVICES

• US 20160246530A1
• Filed: 02/25/2016
• Published: 08/25/2016
• Est. Priority Date: 02/25/2015
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Memory Solutions Incorporated (SK Hynix Inc.)
• Inventors: MYLAVARAPU, Sai Krishna
• Granted Patent: US 10,915,256 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/1471 involving logging of persistent data for recovery
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0632 by initialisation or re-initialisation of storage systems
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

A memory system may include a memory device and a controller. The memory device may include a plurality of storage areas. The controller may be suitable for processing data associated with at least one storage area among the plurality of storage areas of the memory device, and includes a logical to physical (L2P) table suitable for storing logical to physical (L2P) data, and a journal for storing update information indicating a change of logical to physical (L2P) information stored in the L2P table. The memory device may include a logical to physical (L2P) area corresponding to the L2P table of the controller such that, in the event of a power loss, the journal is written to the L2P area of the memory device and restored to the controller when power is restored.

Claims

1. A system comprising:

a memory device including a plurality of storage areas and

a controller suitable for processing data associated with at least one storage area among the plurality of storage areas of the memory device,

wherein the controller includes;

a logical to physical (L2P) table suitable for storing logical to physical (L2P) data, and

a journal for storing update information indicating a change from logical to physical (L2P) information stored in the L2P table, and

wherein the memory device includes a logical to physical (L2P) area corresponding to the L2P table of the controller such that, in the event of a power loss, the journal is written to the L2P area of the memory device and restored to the controller when power is restored.

2. The system of claim 1, wherein the L2P area includes a dedicated area on the memory device operated in a single level cell (SLC) mode.

3. The system of claim 2, wherein the L2P area has a size determined based on a first size for the L2P data and a second size for over provisioning.

5. The system of claim 1, wherein the journal has a size determined based on one of an energy budget and a time budget of the memory device available after accounting for other operations.

6. The system of claim 1, wherein the L2P data is divided into a plurality of chunks.

7. The system of claim 6, wherein each of the plurality of chunks has a size determined based on a super page of the memory device.

8. The system of claim 1, wherein the L2P table is included in a dynamic random access memory (DRAM), and the journal is included in a static random access memory (SRAM).

4. The system of claim wherein the first size includes twice the size for the L2P data.

9. A method for operating a memory system, comprising:

storing logical to physical (L2P) data in a L2P table of a controller,

storing update information in a journal of the controller, the update information indicating a change of L2P stored in the L2P table,

in the event of a power loss, writing the journal to an L2P area of a memory device that corresponds to the L2P table of the controller, and

when power is restored, restoring the journal from the L2P area of the memory device to the controller.

10. The method of claim 9, wherein the L2P area includes a dedicated area on the memory device operated in a single level cell (SLC) mode.

11. The method of claim 10, wherein the L2P area has a size determined based on a first size for the L2P data and a second size for over provisioning.

12. The method of claim 11, wherein the first size includes twice the size for the L2P data.

13. The method of claim 9, wherein the journal has a size determined based on one of an energy budget and a time budget of the memory device available after accounting for other operations.

14. The method of claim 9, wherein the L2P data is divided into a plurality of chunks.

15. The method of claim 14, wherein each of the plurality of chunks has a size determined based on a super page of the memory device.

16. The method of claim 9, wherein the L2P table is included in a dynamic random access memory (DRAM), and the journal is included in a static random access memory (SRAM).