CACHE CONTROLLER FOR NON-VOLATILE MEMORY

• US 20160246724A1
• Filed: 10/31/2013
• Published: 08/25/2016
• Est. Priority Date: 10/31/2013
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Inventors: Boehm, Hans, Chakrabarti, Dhruva
• Granted Patent: US 10,558,569 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/3037 where the computing system component is a memory, e.g. virtual memory, cache accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 12/128 adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G06F 2201/86 Event-based monitoring
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: G06F 2201/885 Monitoring specific for caches
• CPC Class Codes: G06F 2212/202 Non-volatile memory
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

Abstract

Methods, apparatus, systems and articles of manufacture are disclosed to control a cache. An example method includes monitoring cache lines in a cache, the cache lines storing recently written data to the cache, the recently written data corresponding to main memory, comparing a total quantity of the cache lines to a threshold that is less than a cache line storage capacity of the cache, and causing a write back of at least one of the cache lines to the main memory when a store event causes the total quantity of the cache lines to satisfy the threshold.

Claims

1. A method to limit caching comprising:

monitoring cache lines in a cache, the cache lines storing recently written data to the cache, the recently written data corresponding to main memory;

comparing a total quantity of the cache lines to a threshold that is less than a cache line storage capacity of the cache; and

causing a write back of at least one of the cache lines to the main memory when a store event causes the total quantity of the cache lines to satisfy the threshold.

2. A method according to claim 1, wherein the threshold corresponds to at least one of:

a capacity of a data structure storing dirty cache line addresses, or

a cache line capacity of a cache way of the cache, the cache way designated to store cache lines corresponding to only the main memory.

3. A method according to claim 1, wherein the store event does not cause the total quantity of cache lines to increase toward the threshold when the store event modifies a dirty cache line.

4. A method according to claim 1, further comprising:

mapping a read-only memory address space and a writable memory address space; and

when the store event corresponds to the read-only memory address space, performing a store operation at a memory location corresponding to the writable memory address space.

5. A method according to claim 1, further comprising, when processor resources are available;

selecting a second one of the cache lines to be written back to the main memory using a background process before the total quantity of the cache lines satisfies the threshold.

6. A method according to claim 1, wherein the total quantity of the cache lines satisfies the threshold when the total quantity of the cache lines is greater than or equal to the threshold.

7. A machine readable storage medium comprising instructions that, when executed, cause a machine to at least:

monitor cache lines in a cache, the cache lines storing recently written data to the cache, the recently written data corresponding to main memory;

compare a total quantity of the cache lines to a threshold that is less than a cache line storage capacity of the cache; and

cause a write back of at least one of the cache lines to the main memory when a store event causes the total quantity of the cache lines to satisfy the threshold.

8. A machine readable storage medium according to claim 7, wherein the threshold corresponds to at least one of:

a capacity of a data structure storing dirty cache line addresses,

or a cache line capacity of a cache way of the cache, the cache way designated to store cache lines corresponding to only the main memory.

9. A machine readable storage medium according to claim 7, wherein the store event does not cause the total quantity of cache lines to increase toward the threshold when the store event modifies a dirty cache line.

10. A machine readable storage medium according to claim 7, wherein the instructions, when executed further cause the machine to:

map a read-only memory address space and a writable memory address space; and

when the store event corresponds to the read-only memory address space, perform a store operation at a memory location corresponding to the writable memory address space.

11. A machine readable storage medium according to claim 7, wherein the instructions, when executed further cause the machine to:

when processor resources are available, select a second one of the cache lines to be written back to the main memory using a background process before the total quantity of the cache lines satisfies the threshold.

12. An integrated circuit comprising:

a dirty address updater to;

monitor dirty cache lines in a cache, the dirty cache lines storing data to be written back to a non-volatile memory, and

compare a total quantity of the dirty cache lines to a threshold that is less than a cache line storage capacity of the cache; and

a flush indicator to cause a write back of at least one of the dirty cache lines to the non-volatile memory when a store event causes the total quantity of the of dirty cache lines to satisfy the threshold.

13. An integrated circuit according to claim 12, wherein the dirty address updater is to compare the total quantity of the dirty cache lines to the threshold by comparing a quantity of dirty cache line addresses corresponding to the quantity of dirty cache lines to the threshold, wherein the threshold corresponds to a capacity of a data structure storing the dirty cache line addresses.

14. An integrated circuit according to claim 12, wherein the store event does not cause the total quantity of dirty cache lines to increase when the store event modifies a dirty cache line.

15. An integrated circuit according to claim 12, wherein, when processor resources are available, the address updater is select a second one of the dirty cache lines to be written back to the non-volatile memory using a background process before the total quantity of the dirty cache lines satisfies the threshold.