CACHE CONTROLLER FOR NON-VOLATILE MEMORY
First Claim
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1. A method to limit caching comprising:
- monitoring cache lines in a cache, the cache lines storing recently written data to the cache, the recently written data corresponding to main memory;
comparing a total quantity of the cache lines to a threshold that is less than a cache line storage capacity of the cache; and
causing a write back of at least one of the cache lines to the main memory when a store event causes the total quantity of the cache lines to satisfy the threshold.
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Abstract
Methods, apparatus, systems and articles of manufacture are disclosed to control a cache. An example method includes monitoring cache lines in a cache, the cache lines storing recently written data to the cache, the recently written data corresponding to main memory, comparing a total quantity of the cache lines to a threshold that is less than a cache line storage capacity of the cache, and causing a write back of at least one of the cache lines to the main memory when a store event causes the total quantity of the cache lines to satisfy the threshold.
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Citations
15 Claims
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1. A method to limit caching comprising:
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monitoring cache lines in a cache, the cache lines storing recently written data to the cache, the recently written data corresponding to main memory; comparing a total quantity of the cache lines to a threshold that is less than a cache line storage capacity of the cache; and causing a write back of at least one of the cache lines to the main memory when a store event causes the total quantity of the cache lines to satisfy the threshold. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A machine readable storage medium comprising instructions that, when executed, cause a machine to at least:
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monitor cache lines in a cache, the cache lines storing recently written data to the cache, the recently written data corresponding to main memory; compare a total quantity of the cache lines to a threshold that is less than a cache line storage capacity of the cache; and cause a write back of at least one of the cache lines to the main memory when a store event causes the total quantity of the cache lines to satisfy the threshold. - View Dependent Claims (8, 9, 10, 11)
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12. An integrated circuit comprising:
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a dirty address updater to; monitor dirty cache lines in a cache, the dirty cache lines storing data to be written back to a non-volatile memory, and compare a total quantity of the dirty cache lines to a threshold that is less than a cache line storage capacity of the cache; and a flush indicator to cause a write back of at least one of the dirty cache lines to the non-volatile memory when a store event causes the total quantity of the of dirty cache lines to satisfy the threshold. - View Dependent Claims (13, 14, 15)
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Specification