System and Method for Processor-Based Security

• US 20160246736A1
• Filed: 05/27/2014
• Published: 08/25/2016
• Est. Priority Date: 01/16/2009
• Status: Active Grant

• Current Assignee: Coresecure Technologies, LLC
• Original Assignee: Teleputers, LLC
• Inventors: Lee, Ruby B., Champagne, David
• Granted Patent: US 9,784,260 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: F04B 33/00 Pumps actuated by muscle power, e.g. for inflating
• CPC Class Codes: G06F 2009/45587 Isolation or security of virtual machine instances
• CPC Class Codes: G06F 21/57 Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
• CPC Class Codes: G06F 21/575 Secure boot
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects

Abstract

A system and method for processor-based security is provided, for on-chip security and trusted computing services for software applications. A processor is provided having a processor core, a cache memory, a plurality of registers for storing at least one hash value and at least one encryption key, a memory interface, and at least one on-chip instruction for creating a secure memory area in a memory external to the processor, and a hypervisor program executed by the processor. The hypervisor program instructs the processor to execute the at least one on-chip instruction to create a secure memory area for a software area for a software module, and the processor encrypts data written to, and decrypts data read from, the external memory using the at least one encryption key and the verifying data read from the external memory using the at least one hash value. Secure module interactions are provided, as well as the generation of a power-on key which can be used to protect memory in the event of a re-boot event. Lightweight, run-time attestation reports are generated which include selected information about software modules executed by the processors, for use in determining whether the processor is trusted to provide secure services.

Claims

1. A system for providing processor-based security, comprising:

a processor having a processor core, a cache memory, a plurality of registers for storing at least one hash value, and a memory interface; and

at least one on-chip instruction for performing a secure launch of a hypervisor program, the instruction causing the processor to;

compute a first storage hash value over a current state of a first hypervisor program;

compare the first storage hash value to a second storage hash value stored in the plurality of registers;

if the first storage hash value matches the second storage hash value, allow the first hypervisor program corresponding to the first storage hash value to access contents of a secure storage area in a non-volatile memory previously stored by a second hypervisor program corresponding to the second storage hash value; and

if the first storage hash value does not match the second storage hash value, preventing access to the contents stored in the secure storage area and allocating a new secure storage area for the first hypervisor, and copying the first storage hash value into a register containing the second storage hash value,

wherein the processor encrypts and hashes data written to, and decrypts and verifies hashes of data read from, the secure storage area using a first on-chip encryption key and a first on-chip storage hash value,

wherein the processor encrypts and hashes data written to, and decrypts and verifies hashes of data read from, a secure storage area corresponding to a first trusted software module using a second encryption key and a second storage hash value, and

wherein the secure storage area corresponding to the first trusted software module program is defined by a module identity, an encryption key, and a pre-defined storage hash value.

10. The system of claim 1, wherein the second storage hash value is stored in a secure audit or log file before being replaced by a new hash value.

11. The system of claim 1, wherein the first storage hash value and second storage hash value confirm the identity of the first hypervisor program and the machine on which it runs.

14. The system of claim 1, further comprising a power-on key value for protecting a memory external to the processor after a re-boot event, the power-on key value stored in one of the plurality of registers.

15. The system of claim 1, further comprising a plurality of trusted software modules, and at least one command issued to the hypervisor for performing a secure launch of a trusted software module program, the command causing the hypervisor to:

compute a third hash value over a current state of the first trusted software module program;

compare the third hash value to a plurality of hash values stored in the secure storage area of the hypervisor;

if the third hash value matches a fourth hash value in the plurality of hash values, allow the first trusted software module program to access contents of a secure storage area in a non-volatile memory previously stored by a second trusted software module program corresponding to the fourth hash value; and

if the third hash value does not match the fourth hash value, prevent access to the contents stored in the secure storage area and allocate a new secure storage area for the first trusted software program.

18. The system of claim 1, wherein the number of secure storage areas, each associated with a different trusted software module program, is scalable and not limited by a fixed number of hardware registers.

2. (canceled)

3. (canceled)

4. (canceled)

5. A method for providing processor-based security, comprising the steps of:

computing in a processor a first storage hash value using a current state of a first hypervisor program executed by the processor;

comparing the first storage hash value to a second storage hash value stored in one of a plurality of registers of the processor;

if the first storage hash value matches the second storage hash value, allowing the first hypervisor program corresponding to the first storage hash value to access contents of a secure storage area in a non-volatile memory previously stored by a second hypervisor program corresponding to the second storage hash value;

if the first storage hash value does not match the second storage hash value, preventing access to the contents stored in the secure storage area and allocating a new secure storage area for the first hypervisor, and copying the first hash value into a register containing the second storage hash value;

encrypting and hashing data written to, and decrypting and verifying hashes of data read from, the secure storage area using a first on-chip encryption key and a first on-chip storage hash value;

encrypting and hashing data written to, and decrypting and verifying hashes of data read from, a secure storage area corresponding to a first trusted software module using a second encryption key and a second storage hash value; and

defining a secure storage area corresponding to a trusted software module program by a module identity, an encryption key, and a pre-defined storage hash value.

7. The method of claim 5, further comprising generating a power-on key value for protecting a memory external to the processor after a re-boot event, and storing the power-on key value in one of the plurality of registers.

12. The method of claim 5, further comprising storing the second storage hash value in a secure audit or log file before being replaced by a new hash value.

13. The method of claim 5, further comprising using the first storage hash value and second hash value to confirm the identity of the first hypervisor program and the machine on which it runs.

19. The method of claim 5, further comprising the steps of:

computing a third hash value over a current state of the first trusted software module program;

comparing the third hash value to a plurality of hash values stored in the secure storage area of the hypervisor;

if the third hash value matches a fourth hash value in the plurality of hash values, allowing the first trusted software module program to access contents of a secure storage area in a non-volatile memory previously stored by a second trusted software module program corresponding to the fourth hash value; and

if the third hash value does not match the fourth hash value, preventing access to the contents stored in the secure storage area and allocating a new secure storage area for the first trusted software program.

22. The method of claim 5, wherein the number of secure storage areas, each associated with a different trusted software module program, is scalable and not limited by a fixed number of hardware registers.

6. (canceled)

8. (canceled)

9. (canceled)

16. (canceled)

17. (canceled)

20. (canceled)

21. (canceled)