DISPLAY DEVICE AND METHOD OF INSPECTING THE SAME

• US 20160247430A1
• Filed: 12/21/2015
• Published: 08/25/2016
• Est. Priority Date: 02/24/2015
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Cho, Se Hyoung, Kim, Il Gon, Jo, Kang Moon, Kim, Dong Woo, Kim, Kyung Hoon
• Granted Patent: US 9,947,253 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/08 Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
• CPC Class Codes: G09G 2330/10 Dealing with defective pixels
• CPC Class Codes: G09G 2330/12 Test circuits or failure detection circuits included in a display system, as permanent part thereof
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

There are provided a display device capable of detecting a defect of a scan driver. The display device includes pixels positioned in regions demarcated by scan lines and data lines, a scan driver including a plurality of stages connected to the scan lines, an inspection unit connected to the stages to detect whether the stages are defective, and including first transistors turned on when a control signal is supplied, and a timing controller supplying the control signal, wherein the timing controller detects a position of a defective stage by reducing a period during which the control signal is supplied.

Claims

1. A display device comprising:

pixels positioned in regions demarcated by scan lines and data lines;

a scan driver including a plurality of stages connected to the scan lines;

an inspection unit connected to the stages to detect whether the stages are defective, and including first transistors turned on when a control signal is supplied; and

a timing controller supplying the control signal,

wherein the timing controller detects a position of a defective stage by reducing a period during which the control signal is supplied.

2. The display device of claim 1, wherein a first electrode of ith first transistor is connected to an output terminal of ith stage wherein i is a natural number.

3. The display device of claim 2, wherein the inspection unit includes ith second transistor whose first electrode is connected to an output terminal of the ith stage and gate electrode is connected to a second electrode of the ith first transistor.

4. The display device of claim 2, wherein the inspection unit includes ith second transistor whose gate electrode and first electrode are connected to a second electrode of the ith first transistor.

5. The display device of claim 1, wherein the timing controller supplies the control signal during a period in which a scan signal is supplied in every stage, and in response to determining that at least one stage is defective, the timing controller reduces a supply period of the control signal.

6. A display device comprising:

pixels positioned in regions demarcated by scan lines and data lines;

a scan driver including stages connected to the scan lines;

an inspection unit including first transistors respectively connected to the stages to detect whether the stages are defective and second transistors respectively connected to the first transistors and turned on in response to receiving a control signal; and

a timing controller supplying the control signal,

wherein the timing controller detects a position of a defective stage by reducing a period during which the control signal is supplied.

7. The display device of claim 6, wherein a gate electrode of ith first transistor is connected to an output terminal of ith stage, first electrodes of first transistors connected to odd-numbered stages are connected to a first voltage source, and first electrodes of first transistors connected to even-numbered stages are connected to a second voltage source having a voltage different from a voltage of the first voltage source wherein i is a natural number.

8. The display device of claim 7, wherein a first electrode of ith second transistor is connected to a second electrode of the ith first transistor.

9. The display device of claim 6, wherein the timing controller supplies the control signal during a period in which a scan signal is supplied in every stage, and in response to determining that at least one stage is defective, the timing controller reduces a supply period of the control signal.

10. A method of inspecting a display device including stages for supplying a scan signal, the method comprising:

setting first transistors respectively connected between a detect line and the stages to an ON state by supplying a control signal; and

inspecting whether the stages are defective by using a voltage supplied to the detect line,

wherein in response to a determination that at least one of the stages is defective, a position of the defective stage is detected by reducing a supply period of the control signal.

11. The method of claim 10, wherein after inspecting whether the stages are defective, the detect line is cut away from a panel.

12. The method of claim 10, wherein after inspecting whether the stages are defective, the detect line and the first transistors are cut away from the panel.