PATTERN LAYOUT TO PREVENT SPLIT GATE FLASH MEMORY CELL FAILURE

• US 20160247812A1
• Filed: 05/02/2016
• Published: 08/25/2016
• Est. Priority Date: 06/20/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Yu-Hsing, Wu, Chang-Ming, Liu, Shih-Chang
• Granted Patent: US 9,653,471 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a first source/drain region and a second source/drain region. The first and second source/drain regions form a channel region therebetween. The semiconductor structure further includes a select gate and a memory gate spaced between the first and second source/drain regions over the channel region. The select gate extends over the channel region and terminates at a line end having a top surface asymmetric about an axis that extends along a length of the select gate and that bisects a width of the select gate. Even more, the semiconductor structure includes a charge trapping dielectric arranged between neighboring sidewalls of the memory gate and the select gate, and arranged under the memory gate. A method of manufacturing the semiconductor structure is also provided.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate including a pair of source/drain regions laterally spaced along a first axis; and

a pair of gates arranged over the semiconductor substrate between the source/drain regions and laterally spaced along the first axis, wherein the pair of gates comprises a first gate and a second gate, wherein the first gate extends laterally along a second axis that is normal to the first axis and terminates at a line end, and wherein the line end is asymmetric about the second axis.

2. The semiconductor structure according to claim 1, further comprising:

a charge trapping dielectric structure arranged between neighboring sidewalls of the first and second gates, and arranged under the second gate.

3. The semiconductor structure according to claim 1, wherein the first gate has a substantially uniform width while extending to the line end, and wherein the second axis bisects the substantially uniform width.

4. The semiconductor structure according to claim 1, wherein the line end extends laterally between opposing sidewalls, along a third axis that is parallel to the first axis, wherein one of the opposing sidewalls extends along a length of the first gate, and wherein another one of the opposing sidewalls is confined to the line end.

5. The semiconductor structure according to claim 1, wherein the line end extends laterally towards the second gate, along a third axis that is parallel to the first axis.

6. The semiconductor structure according to claim 1, wherein a projection of the line end onto a top surface of the semiconductor substrate is one of circular, triangular, rectangular, square, and trapezoidal.

7. The semiconductor structure according to claim 1, wherein the line end wraps around the second gate and has a distal point that is even with or past a sidewall of the second gate.

8. The semiconductor structure according to claim 1, wherein the semiconductor substrate comprises an additional source/drain region laterally spaced from one of the source/drain regions along the first axis, and wherein the semiconductor structure further comprises:

a third gate and a fourth gate arranged over the semiconductor substrate and laterally spaced along the first axis, wherein the third and fourth gates are arranged between the additional source/drain region and the one of the source/drain regions, wherein the third gate extends laterally along a third axis that is normal to the first axis and that is parallel to the second axis, and wherein the third gate terminates at a second line end that is asymmetric about the third axis and that protrudes away from the first gate.

9. A semiconductor structure comprising:

a memory cell arranged over a semiconductor substrate and comprising a first gate and a second gate laterally spaced along a first axis, wherein the first gate extends laterally along a second axis that crosses the first axis and terminates at a line end, and wherein the line end is asymmetric about the second axis.

10. The semiconductor structure according to claim 9, wherein the second axis crosses the first axis substantially perpendicular to the first axis.

11. The semiconductor structure according to claim 9, further comprising:

a charge trapping dielectric structure arranged between neighboring sidewalls of the first and second gates, and arranged under the second gate.

12. The semiconductor structure according to claim 9, wherein the first gate has a substantially uniform width while extending to the line end, and wherein the second axis bisects the substantially uniform width.

13. The semiconductor structure according to claim 9, wherein the line end extends laterally between opposing sidewalls, along a third axis that is substantially parallel to the first axis, wherein one of the opposing sidewalls extends along a length of the first gate, and wherein another one of the opposing sidewalls is confined to the line end.

14. The semiconductor structure according to claim 9, wherein the line end extends laterally towards the second gate, along a third axis that is substantially parallel to the first axis.

15. The semiconductor structure according to claim 9, wherein a projection of the line end onto a top surface of the semiconductor substrate is one of circular, triangular, rectangular, square, and trapezoidal.

16. The semiconductor structure according to claim 9, wherein the line end wraps around the second gate and has a distal point that is even with or past a sidewall of the second gate.

17. The semiconductor structure according to claim 9, further comprising:

a second memory cell arranged over the semiconductor substrate, laterally adjacent to the memory cell, wherein the second memory cell comprises a third gate and a fourth gate laterally spaced along the first axis, wherein the first gate extends laterally along a third axis that crosses the first axis and terminates at a second line end that is asymmetric about the third axis and that protrudes away from the first and second gates.

18. The semiconductor structure according to claim 17, wherein the second line end is laterally offset from the line end along the third axis.

19. A semiconductor structure comprising:

a first memory cell comprising a first pair of gates arranged over a semiconductor substrate and comprising a first gate laterally spaced from a second gate along a first axis, wherein the first gate extends laterally across the first axis to terminate at a first line end that protrudes laterally in a first direction; and

a second memory cell comprising a second pair of gates arranged over the semiconductor substrate, laterally adjacent to the first pair of gates, wherein the second pair comprises a third gate laterally spaced from a fourth gate along the first axis, wherein third gate extends laterally across the first axis to terminate at a second line end that protrudes laterally in a second direction that is opposite the first direction.

20. The semiconductor structure according to claim 19, wherein the first and second line ends are asymmetric.