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PATTERN LAYOUT TO PREVENT SPLIT GATE FLASH MEMORY CELL FAILURE

  • US 20160247812A1
  • Filed: 05/02/2016
  • Published: 08/25/2016
  • Est. Priority Date: 06/20/2014
  • Status: Active Grant
First Claim
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1. A semiconductor structure comprising:

  • a semiconductor substrate including a pair of source/drain regions laterally spaced along a first axis; and

    a pair of gates arranged over the semiconductor substrate between the source/drain regions and laterally spaced along the first axis, wherein the pair of gates comprises a first gate and a second gate, wherein the first gate extends laterally along a second axis that is normal to the first axis and terminates at a line end, and wherein the line end is asymmetric about the second axis.

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