Integrated Circuit Devices and Methods of Manufacturing the Same

• US 20160247876A1
• Filed: 12/11/2015
• Published: 08/25/2016
• Est. Priority Date: 02/24/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Bo-Cheol Jeong, Hee-Don Jeong, Hwa-Sung Rhee, Hyun-Jo Kim, Jae-Yup Chung, Se-Wan Park, Yoon-Seok Lee
• Inventors: Chung, Jae-yup, LEE, Yoon-seok, KIM, Hyun-jo, JEONG, Hee-don, PARK, Se-wan, JEONG, Bo-cheol, RHEE, Hwa-sung
• Granted Patent: US 9,673,330 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/8232 Field-effect technology
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0843 Source or drain regions of field-effect devices
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 12/056 the transistor being a FinFET

Abstract

An integrated circuit device includes first and second fin-type active regions having different conductive type channel regions, a first device isolation layer covering both sidewalk of the first fin-type active region, and a second device isolation layer covering both sidewalls of the second fin-type active region. The first device isolation layer and the second device isolation layer have different stack structures. To manufacture the integrated circuit device, the first device isolation layer covering both sidewalls of the first fin-type active region and the second device isolation layer covering both sidewalk of the second fin-type active region are formed after the first fin-type active region and the second fin-type active region are formed. The first device isolation layer and the second device isolation layer are formed to have different stack structure.

Claims

1. An integrated circuit device comprising:

a first fin-type active region in a first region of a substrate, the first fin-type active region having a first conductive type channel region;

a first device isolation layer covering both sidewalls of a lower portion of the first fin-type active region;

a second fin-type active region in a second region of the substrate, the second fin-type active region having a second conductive type channel region; and

a second device isolation laser covering both sidewalls of a lower portion of the second fin-type active region;

wherein the first device isolation layer and the second device isolation layer have different stack structures.

2. The integrated circuit device of claim 1, wherein the first fin-type active region is defined by a first trench in the first region,

wherein the first device isolation layer comprises:

a first insulating liner in contact with a sidewall of the first fin-type active region, wherein the first insulating liner is in the first trench; and

a first gapfill insulating layer filling the first trench, wherein the first gapfill insulating layer is on the first insulating liner.

4. The integrated circuit device of claim 2, wherein the second fin-type active region is defined by a second trench in the second region,

wherein the second device isolation layer comprises:

a second insulating liner in contact with a sidewall of the second fin-type active region, wherein the second insulating liner is in the second trench;

a third insulating liner covering a sidewall of the second fin-type active region with the second insulating liner interposed therebetween; and

a second gapfill insulating layer filling the second trench, wherein the second gapfill insulating layer is on the third insulating liner.

3. (canceled)

5. (canceled)

6. An integrated circuit device comprising:

a pair of first fin-type active regions being lined up in a substantially straight line in a first region of a substrate, the pair of first fin-type active regions each having a first conductive type channel region;

a low level first device isolation layer covering both sidewalls of a lower portion of each of the pair of first fin-type active regions;

a high level first device isolation layer extending in a space between fie pair of first fin-type active regions;

a pair of second fin-type active regions being lined up in a substantially straight line in a second region of the substrate, the pair of second fin-type active regions each having a second conductive type channel region;

a low level second device isolation layer covering both sidewalls of a lower portion of each of the pair of second fin-type active regions; and

a high level second device isolation layer extending in a space between the pair of second fin-type active regions;

wherein the low level first device isolation layer and the low level second device isolation layer have different stack structures, and the high level first device isolation layer and the high level second device isolation layer have different stack structures.

7. The integrated circuit device of claim 6, wherein a first fin-type active region of the pair of first fin-type active regions is defined by a first trench in the first region, and a second fin-type active region of the pair of second fin-type active regions is defined by a second trench in the second region,

wherein the low level first device isolation layer comprises:

a first insulating liner in contact with the first fin-type active region; and

a first gapfill insulating layer filling the first trench, wherein the first gapfill insulating layer is on the first insulating liner,

wherein the low level second device isolation layer comprises;

a second insulating liner in contact with the second fin-type active region;

a third insulating liner covering a sidewall of the second fin-type active region with the second insulating liner interposed therebetween; and

a second gapfill insulating layer filling the second trench wherein the second gapfill insulating layer is on the third insulating liner.

8. The integrated circuit device of claim 6, wherein the high level first device isolation layer is in a first fin isolation region between the pair of first fin-type active regions, and the high level second device isolation layer is in a second fin isolation region between the pair of second fin-type active region,

wherein the high level first device isolation layer comprises;

a first insulating liner in contact with the pair of first fin-type active regions;

a first gapfill insulating layer on the first insulating liner; and

a first upper buried layer in contact with the first insulating liner and the first gapfill insulating layer, wherein the first upper buried layer is on the first gapfill insulating layer,

wherein the high level second device isolation layer comprises;

a second insulating liner in contact with the pair of second fin-type active regions;

a third insulating liner on the second insulating liner;

a second gapfill insulating layer on the third insulating liner; and

a second upper buried layer in contact with the second insulating liner, the third insulating liner, and the second gapfill insulating layer, wherein the second upper buried layer is on the second gapfill insulating layer.

9. The integrated circuit device of claim 6, wherein the high level first device isolation layer fills a first fin isolation trench between the pair of first fin-type active regions and tills a first upper trench, wherein the first upper trench has a width larger than that of the first fin isolation trench, is on the first fin isolation trench, and communicates with the first fin isolation trench, and

wherein the high level second device isolation layer fills a second fin isolation trench between the pair of second fin-type active regions and fills a second upper trench, wherein the second upper trench has a width larger than that of the second fin isolation trench, is on the second fin isolation trench, and communicates with the second fin isolation trench.

10. The integrated circuit device of claim 6, wherein the high level first device isolation layer comprises:

a first oxide film in contact with the pair of first fin-type active regions, wherein the first oxide film is in the first fin isolation trench;

a second oxide film filling the first fin isolation trench, wherein the second oxide film is on the first oxide film; and

a third oxide film in contact with the first oxide film and the second oxide film, wherein the third oxide film is in the first upper trench.

11. The integrated circuit device of claim 10, wherein the third oxide film has a width that is greater than that of the first fin isolation trench.

12. The integrated circuit device of claim 9, wherein the high level second device isolation layer comprises:

a fourth oxide film in contact with the pair of second fin type active regions, wherein the fourth oxide film is in the second fin isolation trench;

a fifth oxide film filling the second fin isolation trench, wherein the fifth oxide film is on the fourth oxide film; and

an insulating liner interposed between the fourth oxide film and the fifth oxide film, wherein the insulating liner is in the second fin isolation trench and comprises a material that is different from those of the fourth and fifth oxide films; and

a sixth oxide film in contact with the fourth oxide film, the insulating liner, and the fifth oxide film, wherein the sixth oxide film is in the second upper trench.

14. The integrated circuit device of claim 12, wherein the sixth oxide film has a width that is greater than that of the second fin isolation trench.

15. The integrated circuit device of claim 6, wherein the low level first device isolation layer has an upper surface at a level that is lower than that of an upper surface of each of the pair of first fin-type active regions, the low level second device isolation layer has an upper surface at a level that is lower than that of an upper surf ace of each of the pair of second fin type active regions, the high level first device isolation layer has an upper surface at a level that is higher than that of the upper surface of each of the pairs of first fin-type active regions, and the high level second device isolation layer has an upper surface at a level that is higher than that of the upper surface of each of the pair of second fin-type active regions.

16. The integrated circuit device of claim 6, wherein the low level first device isolation layer has an upper surface at a level that is lower than that of an upper surface of each of the pair of first fin-type active regions, the low level second device isolation layer has an upper surface at a level that is lower than that of an upper surface of each of the pan of second fin-type active regions, the high level first device isolation layer has an upper surface at a level that is substantially the same as that of the upper surface of each of the pair of first fin-type active regions, and the high level second device isolation layer has an upper surface at a level that is substantially the same as that of the upper surface of each of the pair of second fin-type active regions.

17. The integrated circuit device of claim 6, further comprising:

a first normal gate on a first fin-type active region of the pair of first fin-type active regions, and extending in a direction intersecting with an extending direction of the pair of first fin-type active regions; and

a first dummy gate on the high level first device isolation layer, and extending parallel to the at least one first normal gate.

19. The integrated circuit device of claim 6, further comprising:

a second normal gate on a second fin-type active region of the pair of second fin-type active regions, and extending in a direction intersecting with an extending direction of the pair of second fin-type active regions; and

a second dummy gate on the high level second device isolation layer, and extending parallel to the at least one second normal gate.

13. (canceled)

18. (canceled)

20-31. -31. (canceled)

32. An integrated circuit device comprising;

a substrate comprising a first region and a second region,

wherein the first region and the second region have different conductivity types from one another;

a plurality of first fin-type active regions in the first region and extending in a first direction,

wherein adjacent first fin-type active regions of the plurality of first fin-type active regions are separated by respective first trenches,

wherein the first trench is filled with a first stack comprising a first insulating liner and a first gapfill insulating layer, and

wherein the first insulating liner conformally covers the first trench and the first gapfill insulating layer covers the first insulating liner; and

a plurality of second fin-type active regions in the second region and extending in the first direction,

wherein adjacent second fin-type active regions of the plurality of second fin-type active regions are separated by respective second trenches,

wherein the second trench is filled with a second stack comprising a second insulating liner, a third insulating liner and a second gapfill insulating layer, and

wherein the second insulating liner conformally covers the second trench, the third insulating liner covers the second insulating liner and the second gapfill insulating layer covers the third insulating liner.

33. The integrated circuit device of claim 32 further comprising

a third trench in the first region extending in a second direction perpendicular to the first direction and intersecting individual ones of the plurality of first fin-type active regions, wherein the third trench has a depth substantially the same as a level of bottoms of the plurality of first fin-type active regions;

a fourth trench in the first region extending in the second direction and above the third trench, wherein a depth of the fourth trench is less than the depth of the third trench, and wherein a width of the fourth trench is greater than a width of the third trench;

a fifth trench in the second region extending in the second direction and intersecting individual ones of the plurality of second fin-type active regions, wherein the fifth trench has a depth substantially the same as a level of bottoms of the plurality of second fin-type active regions;

a sixth trench in the second region extending in the second direction and above the fifth trench, wherein a depth of the sixth trench is less than the depth of the fifth trench, and wherein a width of the sixth trench is greater than a width of the fifth trench,

wherein the third trench is filled with a third stack comprising the first insulating liner and the first gapfill insulating layer, wherein the first insulating liner conformally covers the third trench and the first gapfill insulating layer covers the first insulating liner,

wherein the fourth trench is filled with a first buried layer above, and in contact with, the first insulating liner and the first gapfill insulating layer,

wherein the fifth trench is filled with a fourth stack comprising the second insulating liner, the third insulating liner and the second gapfill insulating layer, wherein the second insulating liner conformally covers the fifth trench, the third insulating liner covers the second insulating liner and the second gapfill insulating layer covers the third insulating liner, and

wherein the sixth trench is filled with a second buried layer above, and in contact with, the second insulating liner, the third insulating liner, and the second gapfill insulating layer.

34. The integrated circuit device of claim 33 wherein a level of an upper surface of the first buried layer is substantially the same as upper surfaces of the plurality of first fin-type active regions, and

wherein, a level of an upper surface of the second buried layer is substantially the same as upper surfaces of the plurality of second fin-type active regions.

35. The integrated circuit device of claim 33 wherein a level of an upper surface of the first buried layer is above upper surfaces of the plurality of that fin-type active regions, and

wherein a level of an upper surface of the second buried layer is above upper surfaces of the plurality of second fin-type active regions.

36. The integrated circuit device of claim 34, further comprising;

a first source/drain region in a first one of the plurality of first fin-type active regions,

wherein the first source/drain region contacts the first insulating layer and the first buried layer, and wherein an upper surface of the first source/drain region is above the level of the upper surface of the first buried layer; and

a second source/drain region in a second one of the plurality of second fin-type active regions,

wherein the second source/drain region contacts the second insulating liner and the second buried layer, and wherein an upper surface of the second source/drain region is above the level of the upper surface of the second buried layer.