SILICON CARBIDE SEMICONDUCTOR DEVICE

• US 20160247910A1
• Filed: 09/15/2014
• Published: 08/25/2016
• Est. Priority Date: 10/02/2013
• Status: Active Grant

• Current Assignee: DENSO Corporation, Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Original Assignee: DENSO Corporation, Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Inventors: SUZUKI, Naohiro, AOI, Sachiko, WATANABE, Yukihiko, SOENO, Akitaka, KONISHI, Masaki
• Granted Patent: US 9,647,108 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A silicon carbide semiconductor device includes: a substrate; a drift layer; a current dispersion layer; a base region; a source region; trenches; a gate insulation film; a gate electrode; a source electrode; a drain electrode; and a bottom layer. The current dispersion layer is arranged on the drift layer, and has a first conductive type with an impurity concentration higher than the drift layer. The bottom layer has a second conductive type, is arranged under the base region, covers a bottom of each trench including a corner portion of the bottom of the trench, and has a depth equal to or deeper than the current dispersion layer.

Claims

1. A silicon carbide semiconductor device comprising:

an inversion type MOSFET, wherein;

the MOSFET includes;

a substrate made of silicon carbide and having a first conductive type or a second conductive type;

a drift layer made of silicon carbide, arranged on the substrate, and having the first conductive type with an impurity concentration lower than the substrate;

a current dispersion layer made of silicon carbide, arranged on the drift layer, and having the first conductive type with an impurity concentration higher than the drift layer;

a base region made of silicon carbide, arranged on the current dispersion layer, and having the second conductive type;

a source region made of silicon carbide, arranged in an upper portion of the base region, and having the first conductive type with an impurity concentration higher than the drift layer;

a plurality of trenches arranged from a surface of the source region to a position deeper than the base region, arranged in parallel to each other, and having a stripe shape along one direction as a longitudinal direction;

a gate insulation film arranged on an inner wall of each trench;

a gate electrode arranged on the gate insulation film in each trench;

a source electrode electrically connected to the source region and the base region;

a drain electrode arranged on a back side of the substrate; and

a bottom layer arranged under the base region, covering a bottom of each trench including a corner portion of the bottom of the trench, having a depth equal to or deeper than the current dispersion layer, and having the second conductive type;

the MOSFET provides an inversion type channel region in a surface portion of the base region, which is disposed on a sidewall of the trench, by controlling an application voltage to the gate electrode; and

the MOSFET flows current between the source electrode and the drain electrode through the source region, the current dispersion layer and the drift layer.

2. The silicon carbide semiconductor device according to claim 1, wherein:

the current dispersion layer is arranged to a position deeper than the bottom of the trench.

3. The silicon carbide semiconductor device according to claim 1, further comprising:

a deep layer having the second conductive type, arranged between adjacent two trenches among the plurality of trenches arranged in parallel to each other, contacting the base region, and reaching the drift layer.

4. The silicon carbide semiconductor device according to claim 3, wherein:

an impurity concentration of the bottom layer and an impurity concentration of the deep layer are set not to fully deplete with a depletion layer, which expands from a boundary of the current dispersion layer, when a voltage is applied to the drain electrode in an inversion bias manner.

5. The silicon carbide semiconductor device according to claim 4, wherein:

the impurity concentration of the bottom layer and the impurity concentration of the deep layer are higher twice than an impurity concentration of the current dispersion layer.

6. The silicon carbide semiconductor device according to claim 1, wherein:

the base region includes a first layer disposed on a source region side and a second layer disposed on a current dispersion layer side; and

the second layer has an impurity concentration higher than the first layer.

7. The silicon carbide semiconductor device according to claim 1, wherein:

an impurity concentration of the current dispersion layer is set to make a distance between the base region and the bottom layer larger twice than a distance of a depletion layer expanding in the current dispersion layer by an inner electric potential of silicon carbide.

8. The silicon carbide semiconductor device according to claim 7, wherein:

a dielectric constant of vacuum is defined as ∈

₀;

an elementary charge is defined as q;

a relative dielectric constant of silicon carbide is defined as Ks;

an inner electric potential of silicon carbide is defined as ψ

d; and

the distance of the depletion layer expanding in the current dispersion layer by the inner electric potential of silicon carbide is calculated by an equation No. 1 of;