DECISION FEEDBACK EQUALIZATION

• US 20160248608A1
• Filed: 02/19/2015
• Published: 08/25/2016
• Est. Priority Date: 02/19/2015
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Fiedler, Alan S.
• Granted Patent: US 9,455,846 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/062 Setting decision thresholds using feedforward techniques only
• CPC Class Codes: H04L 7/0045 Correction by a latch cascade
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A signal sampling system that includes N samplers is disclosed. Each sampler includes a data input having a decision logic level threshold, a plurality of offset control inputs, a plurality of offset magnitude inputs, an un-buffered output, and a buffered output. Each sampler further includes circuitry coupled between the inputs and outputs that is configured to cause a time delay from an input signal transition to an output signal transition such that, after an offset control input transitions from a first voltage to a second voltage, the decision logic level threshold changes in a time substantially less than one gate delay, and after the sample clock transitions from a first logic state to a second logic state, the un-buffered output transitions within a time substantially equal to one gate delay and the buffered output transitions within a time substantially equal to two gate delays.

Claims

1. A signal sampling system comprising N latching samplers, wherein

N is an integer equal to or greater than four;

each sampler of the N latching samplers includes a sample clock input to couple to a sample clock, and the sample clocks of the N latching samplers are spaced in phase through 360 degrees;

each sampler of the N latching samplers further includes a data input having a decision logic level threshold, a plurality of offset control inputs, a plurality of offset magnitude inputs, an un-buffered output, and a buffered output; and

each sampler of the N latching samplers further includes circuitry coupled between the inputs and outputs that causes a time delay from an input signal transition to an output signal transition wherein,

after an offset control input changes from a first voltage to a second voltage, the decision logic level threshold changes in a time less than one gate delay, and

after the sample clock transitions from a first logic state to a second logic state, the un-buffered output transitions within a time substantially equal to one gate delay and the buffered output transitions within a time substantially equal to two gate delays.

2. The signal sampling system of claim 1, wherein for X ranging from 0 to N−

1,

sampler X is coupled to a sample clock having a frequency and having a phase of X*360/N degrees;

the plurality of offset control inputs includes a first offset control input and the plurality of offset magnitude inputs includes a first offset magnitude input; and

the un-buffered output of sampler X is coupled to the first offset control input of sampler X+1 modulo N+1.

3. The signal sampling system of claim 2, wherein

the plurality of offset control inputs further includes a second offset control input and the plurality of offset magnitude inputs includes a second offset magnitude input;

and

the buffered output of sampler X is coupled to the second offset control input of sampler X+2 modulo N+1.

4. The signal sampling system of claim 3, wherein

N is an integer equal to or greater than six;

the plurality of offset control inputs further includes offset control inputs 3 to integer N/2;

the plurality of offset magnitude inputs further includes offset magnitude inputs 3 to integer N/2; and

the buffered output of sampler X is coupled to offset control input Y of samplers X+Y modulo N+1, wherein Y ranges from 3 to integer N/2.

5. The signal sampling system of claim 4, wherein

a voltage source is coupled to each of the first and second offset magnitude inputs, and to each of the other offset magnitude inputs from 3 to integer N/2 offset magnitude inputs;

and

the decision logic level threshold for each sampler of the N latching samplers is controlled by a combined action of the offset control inputs and offset magnitude inputs of the sampler of the N latching samplers.

6. The sampling system of claim 5, wherein

for each latching sampler of the N latching samplers, when the sample clock transitions from low to high and the data input signal is greater than the decision logic level threshold of the sampler of the N latching samplers, the un-buffered and buffered outputs transition to a logic high level;

and

for each latching sampler of the N latching samplers, when the sample clock transitions from low to high and the data input signal is less than the decision logic level threshold of that sampler of the N latching samplers, the un-buffered and buffered outputs transition to a logic low level.

7. The signal sampling system of claim 6, wherein each sampler of the N latching samplers further includes a registered output and a slave latch coupled between the buffered output and the registered output.

8. The signal sampling system of claim 7, wherein

the un-buffered output, buffered output and registered output of each sampler of the N latching samplers are configured to utilize complementary signaling;

and

the offset control inputs and data input of each sampler of the N latching samplers are configured to utilize differential signaling.

9. A signal sampling system, comprising

N latching samplers, wherein N is an integer equal to or greater than four;

and

a decision feedback equalizer providing communication between the N latching samplers, the decision feedback equalizer comprising, for each sampler of the N latching samplers,

integer N/2 offset control inputs and integer N/2 offset magnitude inputs that are configured to provide feedback to adjust a decision logic level threshold for the latching sampler of the N latching samplers, wherein

a first offset control input of the integer N/2 offset control inputs is coupled to an un-buffered sampler output of one or more other samplers of the N latching samplers, and

a second offset control input of the integer N/2 offset control inputs is coupled to a buffered sampler output of one or more other samplers of the N latching samplers.

10. The signal sampling system of claim 9, wherein

each offset control input is driven by an offset control signal;

each offset magnitude input is driven by an offset magnitude voltage;

the offset magnitude input signal is set by a digital value; and

the decision logic level threshold is determined by a combined action of the offset control signals and the offset magnitude voltages.

11. The signal sampling system of claim 10, wherein for X ranging from 0 to N−

1,

sampler X is coupled to a sample clock having a frequency and having a phase of X*360/N degrees;

the un-buffered output of sampler X is coupled to the first offset control input of sampler X+1 modulo N+1; and

the buffered output of sampler X is coupled to the second offset control input of sampler X+2 modulo N+1.

12. The signal sampling system of claim 11, wherein

N is an integer equal to or greater than six;

and

for X ranging from 0 to N−

1, the buffered output of sampler X is coupled to a third offset control input of sampler X+3 modulo N+1.

13. The sampling system of claim 12, wherein,

for each sampler of the N latching samplers, when the sample clock transitions from low to high and the data input signal is greater than the decision logic level threshold of the sampler of the N latching samplers, the un-buffered and buffered outputs are configured to transition to a logic high level, and

for each sampler of the N latching samplers, when the sample clock transitions from low to high and the data input signal is less than the decision logic level threshold of the sampler of the N latching samplers, the un-buffered and buffered outputs are configured to transition to a logic low level.

14. A method of operating a signal sampling system including N latching samplers, the method comprising:

for each sampler of the N latching samplers,

receiving, at each of a plurality of offset control inputs, a buffered output signal or an un-buffered output signal from another sampler of the N latching samplers;

receiving, at each of a plurality of offset magnitude inputs, an offset magnitude signal, the offset magnitude signal indicating an amount of contribution from a respective offset control input to an adjustment of a decision logic level threshold of the sampler;

adjusting the decision logic level threshold of the sampler based at least one of the signals received at the plurality of offset control inputs and the plurality of offset magnitude signals received at the plurality of offset magnitude inputs, where the decision logic level threshold changes within a time less than one gate delay after an offset control input of the sampler transitions from a first voltage to a second voltage;

receiving, at a data input of the sampler, a data signal; and

sampling the data signal as a logic level based on a comparison of the data signal to the decision logic level threshold.

15. The method of claim 14, further comprising, for each sampler of the N latching samplers, providing a plurality of un-buffered output signals and a plurality of buffered output signals to one or more other samplers of the N latching samplers, where the un-buffered output signal transitions within a time substantially equal to one gate delay after the sample clock transitions from a first logic level to a second logic level, and where the buffered output signal transitions within a time substantially equal to two gate delays after the sample clock transitions from the first logic level to the second logic level.

16. The method of claim 15, wherein for X ranging from 0 to N−

1, the method further comprises providing the un-buffered output signal of sampler X to an offset control input of sampler X+1 modulo N+1.

17. The method of claim 15, wherein for X ranging from 0 to N−

1, the method further comprises providing the buffered output signal of sampler X to an offset control input of sampler X+2 modulo N+1.

18. The method of claim 17, wherein N is an integer equal to or greater than six, and wherein the method further comprises providing the buffered output of sampler X to an offset control input of samplers X+Y modulo N+1, wherein Y ranges from 3 to integer N/2.

19. The method of claim 18, further comprising, for each sampler of the N latching samplers, transitioning the un-buffered and buffered output signals of the sampler of the N latching samplers to a logic high level when a sample clock that is input to the sampler transitions from low to high and the data input signal is greater than the decision logic level threshold of the sampler of the N latching samplers.

20. The method of claim 18, further comprising, for each sampler of the N latching samplers, transitioning the un-buffered and buffered output signals of the sampler of the N latching samplers to a logic low level when a sample clock that is input to the sampler transitions from low to high and the data input signal is less than the decision logic level threshold of the sampler of the N latching samplers.