Method of Forming Layout Design

• US 20160254190A1
• Filed: 05/09/2016
• Published: 09/01/2016
• Est. Priority Date: 09/12/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Zhuang, Hui-Zhong, Hsieh, Tung-Heng, Lin, Chung-Te, Wang, Sheng-Hsiung, Chiang, Min-Hsiung, Chiang, Ting-Wei, Tien, Li-Chun
• Granted Patent: US 9,899,263 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: H01L 21/3043 Making grooves, e.g. cutting
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch.

Claims

1. A method of manufacturing an integrated circuit (IC), the method comprising:

forming a plurality of gate structures, wherein at least one segment of the plurality of gate structures corresponds to a transistor to be subject to an electrical characteristic tuning process, the plurality of gate structures extending along a first direction and having a predetermined pitch measurable along a second direction, the predetermined pitch being smaller than a spatial resolution of a lithographic technology used to form the plurality of gate structures;

depositing an insulating layer over the plurality of gate structures; and

forming one or more openings in the insulating layer, the one or more openings having a width measurable along the second direction, the width of the respective openings being less than twice the predetermined pitch.

2. The method of claim 1, further comprising cutting at least one of the plurality of gate structures into two gate structures.

3. The method of claim 1, wherein each of the plurality of gate structures extends over one or more fin structures.

4. The method of claim 1, further comprising applying an electrical characteristic tuning process to the transistor to be subject to an electrical characteristic tuning process.

5. The method of claim 4, wherein the electrical characteristic tuning process is selected from the group consisting of adjusting threshold voltage, adjusting turn-on current, or adjusting leakage current.

6. The method of claim 4, wherein the electrical tuning process is selected from the group consisting of increasing an effective doping concentration of a fin structure relative to other fin structures not subjected to the electrical tuning process, decreasing an effective doping concentration of a fin structure relative to other fin structures not subjected to the electrical tuning process, and decreasing a width of a fin structure relative to other fin structures not subjected to the electrical tuning process.

7. The method of claim 4, wherein the electrical tuning process includes forming a gate electrode having a first work function for the transistor to be subject to the electrical characteristic tuning process and selecting and forming a gate electrode having a second work function, different than the first work function, for a second transistor not to be subjected to the electrical characteristic tuning process.

8. The method of claim 1, wherein at least one of the plurality of gate structures is a dummy gate structure overlapping a boundary between adjacent logic cells.

9. The method of claim 1, wherein the plurality of gate structures are formed using a multiple-patterning process.

10. A method of manufacturing an integrated circuit (IC), the method comprising:

forming a plurality of transistors, the plurality of transistors comprising a plurality of source regions, a plurality of drain regions, and a plurality of gate structures overlying respective source regions and drain regions, the plurality of gate structures each extending along a first direction and having a predetermined pitch measurable along a second direction, the predetermined pitch being smaller than a spatial resolution of a lithographic technology used to form the plurality of gate structures;

selecting a subset of the plurality of transistors for a tuning process;

forming a patterned layer on the plurality of transistors, the patterned layer including a repeating pattern of features, the width of the features being less than twice the predetermined pitch; and

performing the tuning process on the subset of transistors.

11. The method of claim 10, wherein the step of forming a patterned layer on the plurality of transistors includes forming a repeating pattern of openings in the patterned layer.

12. The method of claim 10, wherein the step of forming a patterned layer on the plurality of transistors includes forming a repeating pattern of masking features in the patterned layer.

13. The method of claim 10, further comprising forming the plurality of gate structures using a multiple-patterning process.

14. The method of claim 10, wherein the subset of the plurality of transistors are dummy transistors formed at a boundary between adjacent logic cells.

15. The method of claim 10, wherein the tuning process is selected from the group consisting of adjusting threshold voltage, adjusting turn-on current, or adjusting leakage current.

16. The method of claim 10, wherein the tuning process is selected from the group consisting of increasing an effective doping concentration of the subset of transistors, decreasing an effective doping concentration of the subset of transistors, decreasing a width of a fin structure of the subset of transistors relative to other fin structures not in the subset of transistors, and forming a gate electrode having a first work function for the subset of transistors and forming a gate electrode having a second work function, different than the first work function, for transistors not in the subset of transistors.

17. The method of claim 10, further comprising cutting at least one of the plurality of gate structures to form two gate structures extending along the first direction.

18. The method of claim 10, wherein each of the plurality of gate structures extends over one or more fin structures.

19. A method comprising:

using a multiple patterning process, forming a plurality of gate structures, the plurality of gate structures extending along a first direction and having a predetermined pitch measurable along a second direction;

depositing an insulating layer over the plurality of gate structures;

forming one or more openings in the insulating layer, the one or more openings having a width measurable along the second direction, the width of the respective openings being less than twice the predetermined pitch; and

performing an electrical characteristic tuning process on transistor structures exposed by the one or more openings.

20. The method of claim 19, wherein the electrical characteristic tuning process is selected from the group consisting of adjusting threshold voltage, adjusting turn-on current, or adjusting leakage current.