ADJACENT DEVICE ISOLATION

• US 20160254261A1
• Filed: 02/26/2015
• Published: 09/01/2016
• Est. Priority Date: 02/26/2015
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: MACHKAOUTSAN, Vladimir, BADAROGLU, Mustafa, XU, Jeffrey Junhao, SONG, Stanley Seungchul, YEAP, Choh Fei
• Granted Patent: US 9,502,414 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/321 After treatment
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0642 Isolation within the component, i.e. internal isolation
• CPC Class Codes: H01L 29/0669 Nanowires or nanotubes carbon nanotubes as material of solid-state device active part H10K85/211
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 : with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 : using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66803 : with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An integrated circuit (IC) device may include a first active transistor of a first-type in a first-type region. The first active transistor may have a first-type work function material and a low channel dopant concentration in an active portion of the first active transistor. The IC device may also include a first isolation transistor of the first-type in the first-type region. The second active transistor may have a second-type work function material and the low channel dopant concentration in an active portion of the first isolation transistor. The first isolation transistor may be arranged adjacent to the first active transistor.

Claims

1. An integrated circuit (IC) device, comprising:

a first active transistor of a first-type in a first-type region, having a first-type work function material and a channel dopant concentration in an active portion of the first active transistor; and

a first isolation transistor of the first-type in the first-type region having a second-type work function material and the channel dopant concentration in an active portion of the first isolation transistor, the first isolation transistor being adjacent to the first active transistor.

2. The IC device of claim 1, further comprising

a second active transistor of a second-type in a second-type region, having the second-type work function material;

and

a second isolation transistor of the second-type in the second-type region having the first-type work function material, the second active transistor being adjacent to the second isolation transistor.

3. The IC device of claim 1, further comprising a third active transistor adjacent to the first isolation transistor in the first-type region, the third active transistor being electrically isolated from the first active transistor by the first isolation transistor, having a higher threshold voltage than the first active transistor and the third active transistor.

4. The IC device of claim 1, in which a gate of the first isolation transistor is biased to place the first isolation transistor in an OFF state.

5. The IC device of claim 1, in which the first-type is an n-type and the first-type region is an n-type region and the second-type work function material is a p-type work function material, and

in which the first isolation transistor is disposed in the n-type region with the p-type work function material to provide a higher threshold voltage than the first active transistor.

6. The IC device of claim 1, in which the first active transistor and the first isolation transistor comprise a fin field-effect transistor (FinFET) and the active portion comprises a fin of the FinFET.

7. The IC device of claim 6, in which a first active FinFET and a first isolation FinFET comprise an active fin portion on a doped fin portion, the doped fin portion doped with a solid state dopant.

8. The IC device of claim 1, in which the first active transistor and the first isolation transistor comprise a gate-all-around nanowire field-effect transistor (FET).

9. The IC device of claim 1 integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

10. A method for altering a work function material of an isolation transistor within an integrated circuit (IC) device, the method comprising:

exposing a first-type work function material of the isolation transistor disposed adjacent to a first-type active transistor in a first-type region;

etching the first-type work function material of the isolation transistor to form a second-type work function material for the isolation transistor within the first-type region; and

depositing a conductive fill material on the second-type work function material of the isolation transistor.

11. The method of claim 10, further comprising biasing a gate of the isolation transistor is to place the isolation transistor in an OFF state.

12. The method of claim 10, further comprising doping a source/drain portion of the first-type active transistor and the isolation transistor using a solid state dopant.

13. The method of claim 10, in which exposing comprises:

depositing a mask to define openings to the isolation transistor within alternating n-type regions and p-type regions; and

performing a strip resist process to expose the isolation transistor within the alternating n-type regions and p-type regions.

14. The method of claim 10, in which the IC device is integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

15. An integrated circuit (IC) device, comprising:

a first active transistor of a first-type in a first-type region, having a first-type work function material and a channel dopant concentration in an active portion of the first active transistor, the active portion comprising an active fin portion on a doped fin portion; and

a first means for isolating the first active transistor, the first isolating means being adjacent to the first active transistor.

16. The IC device of claim 15, further comprising

a second active transistor of a second-type in a second-type region, having a second-type work function material;

and

a second means for isolating the second active transistor, the second active transistor being adjacent to the second isolating means.

17. The IC device of claim 15, further comprising a third active transistor adjacent to the first isolating means in the first-type region, the third active transistor being electrically isolated from the first active transistor by the first isolating means, having a higher threshold voltage than the first active transistor and the third active transistor.

18. The IC device of claim 15, in which the first isolating means comprises a first isolation transistor of the first-type in the first-type region having a second-type work function material and the channel dopant concentration in an active portion of the first isolation transistor, and a gate of the first isolation transistor is biased to place the first isolation transistor in an OFF state.

19. The IC device of claim 15, in which the first-type is an n-type and the first-type region is an n-type region and a second-type work function material is a p-type work function material, and

in which the first isolating means comprises a first isolation transistor disposed in the n-type region with the p-type work function material to provide a higher threshold voltage than the first active transistor.

20. The IC device of claim 19, in which the first active transistor and the first isolation transistor comprise a fin field-effect transistor (FinFET) and the active portion comprises a fin of the FinFET.

21. The IC device of claim 20, in which a first active FinFET and a first isolation FinFET comprise the active fin portion on the doped fin portion, the doped fin portion doped with a solid state dopant.

22. The IC device of claim 15, in which the first isolating means comprises a first isolation transistor and in which the first active transistor and the first isolation transistor comprise a gate-all-around nanowire field-effect transistor (FET).

23. The IC device of claim 15 integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

24. A method for altering a work function material of an isolation transistor within an integrated circuit (IC) device, the method comprising:

the step for exposing a first-type work function material of the isolation transistor disposed adjacent to a first-type active transistor in a first-type region;

the step for etching the first-type work function material of the isolation transistor to form a second-type work function material for the isolation transistor within the first-type region; and

the step for depositing a conductive fill material on the second-type work function material of the isolation transistor.

25. The method of claim 24, further comprising the step for biasing a gate of the isolation transistor is to place the isolation transistor in an OFF state.

26. The method of claim 24, further comprising the step for doping a source/drain portion of the first-type active transistor and the isolation transistor using a solid state dopant.

27. The method of claim 24, in which the step for exposing comprises:

the step for depositing a mask to define openings to the isolation transistor within alternating n-type regions and p-type regions; and

the step for performing a strip resist process to expose the isolation transistor within the alternating n-type regions and p-type regions.

28. The method of claim 24, in which the IC device is integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.