MAGNETIC RANDOM ACCESS MEMORY (MRAM) BIT CELLS EMPLOYING SOURCE LINES (SLs) AND/OR BIT LINES (BLs) DISPOSED IN MULTIPLE, STACKED METAL LAYERS TO REDUCE MRAM BIT CELL RESISTANCE

• US 20160254318A1
• Filed: 09/16/2015
• Published: 09/01/2016
• Est. Priority Date: 02/27/2015
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Lu, Yu, Zhu, Xiaochun, Kang, Seung Hyuk
• Application Number:
  US14/856,316
• Publication Number:
  US 20160254318A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

Magnetic random access memory (MRAM) bit cells employing source lines and/or bit lines disposed in multiple, stacked metal layers to reduce MRAM bit cell resistance are disclosed. Related methods and systems are also disclosed. In aspects disclosed herein, MRAM bit cells are provided in a memory array. The MRAM bit cells are fabricated in an integrated circuit (IC) with source lines and/or bit lines formed by multiple, stacked metal layers disposed above a semiconductor layer to reduce the resistance of the source lines. In this manner, if node size in the IC is scaled down, the resistance of the source lines and/or the bit lines can be maintained or reduced to avoid an increase in drive voltage that generates a write current for write operations for the MRAM bit cells.

Claims

1. An integrated circuit (IC) comprising at least one magnetic random access memory (MRAM) bit cell, the at least one MRAM bit cell, comprising:

an access transistor disposed in a semiconductor layer of the IC, the access transistor comprising a gate, a source, and a drain;

a magnetic tunnel junction (MTJ) disposed in a metal layer in the IC disposed above the semiconductor layer, the MTJ comprising a first end electrode and a second end electrode;

a drain-side connection column disposed in at least one metal layer in the IC above the semiconductor layer coupling the drain of the access transistor to the first end electrode of the MTJ;

a bit line disposed in at least one metal layer in the IC above the semiconductor layer coupled to the second end electrode of the MTJ; and

a source line disposed in a plurality of stacked metal layers in the IC above the semiconductor layer and coupled to the source of the access transistor.

2. The IC of claim 1, wherein the source line comprises a plurality of stacked metal lines disposed in the plurality of stacked metal layers and electrically coupled together.

3. The IC of claim 2, wherein at least two metal lines among the plurality of stacked metal lines of the source line have different lengths from each other.

4. The IC of claim 2, wherein at least two metal lines among the plurality of stacked metal lines of the source line have different widths from each other.

5. The IC of claim 2, wherein at least two metal lines among the plurality of stacked metal lines of the source line have different lengths and widths from each other.

6. The IC of claim 2, further comprising at least one elongated via disposed in the IC between at least two metal lines among the plurality of stacked metal lines of the source line, the at least one elongated via electrically coupling the at least two metal lines among the plurality of stacked metal lines of the source line together.

7. The IC of claim 1, wherein the bit line is disposed in a plurality of stacked metal layers in the IC disposed above the semiconductor layer.

8. The IC of claim 7, wherein the bit line comprises a plurality of stacked metal lines disposed in the plurality of stacked metal layers and electrically coupled together.

9. The IC of claim 8, wherein at least two metal lines among the plurality of stacked metal lines of the bit line have different lengths and widths from each other.

10. The IC of claim 8, further comprising at least one elongated via disposed in the IC between at least two metal lines among the plurality of stacked metal lines of the bit line, the at least one elongated via electrically coupling the at least two metal lines among the plurality of stacked metal lines of the bit line together.

11. The IC of claim 1, further comprising at least one MRAM dedicated metal layer disposed in the IC, wherein the bit line is disposed in the at least one MRAM dedicated metal layer.

12. The IC of claim 1, wherein:

the at least one MRAM bit cell comprises a plurality of MRAM bit cells; and

the bit line is comprised of a shared bit line coupled between the first end electrode of the MTJs of the plurality of MRAM bit cells and the drain of each access transistor of the plurality of MRAM bit cells.

13. The IC of claim 1, wherein a resistance of the source line and a resistance of the bit line are approximately equal resistances.

14. The IC of claim 1, wherein the MTJ further comprises:

a tunnel barrier between the first end electrode and the second end electrode;

a free layer between the second end electrode and the tunnel barrier; and

a pinned layer between the first end electrode and the tunnel barrier.

15. The IC of claim 1, further comprising a word line disposed in the IC, wherein the word line is coupled to the gate of the access transistor.

16. The IC of claim 1, wherein the at least one MRAM bit cell is comprised of at least one 1T-1MTJ MRAM bit cell.

17. The IC of claim 1, wherein the at least one MRAM bit cell is comprised of at least one 2T-1MTJ MRAM bit cell.

18. The IC of claim 1, wherein the at least one MRAM bit cell is comprised of at least one 2T-2MTJ MRAM bit cell.

19. The IC of claim 1, wherein the at least one MRAM bit cell comprises a plurality of MRAM bit cells in an MRAM array.

20. The IC of claim 1 integrated into a device selected from the group consisting of:

a set top box;

an entertainment unit;

a navigation device;

a communications device;

a fixed location data unit;

a mobile location data unit;

a mobile phone;

a cellular phone;

a computer;

a portable computer;

a desktop computer;

a personal digital assistant (PDA);

a monitor;

a computer monitor;

a television;

a tuner;

a radio;

a satellite radio;

a music player;

a digital music player;

a portable music player;

a digital video player;

a video player;

a digital video disc (DVD) player; and

a portable digital video player.

21. A method of fabricating a magnetic random access memory (MRAM) bit cell in an integrated circuit (IC), comprising:

forming an access transistor in a semiconductor layer, the access transistor comprising a gate, a source, and a drain;

forming a magnetic tunnel junction (MTJ) in a metal layer disposed above the semiconductor layer, the MTJ comprising a first end electrode and a second end electrode;

forming a drain-side connection column in at least one metal layer in the IC above the semiconductor layer coupling the drain of the access transistor to the first end electrode of the MTJ;

forming a bit line in at least one metal layer above the semiconductor layer coupled to the second end electrode of the MTJ; and

forming a source line in a plurality of stacked metal layers in the IC above the semiconductor layer coupled to the source of the access transistor.

22. The method of claim 21, wherein forming the source line comprises forming the source line in a plurality of stacked metal lines electrically coupled together in the plurality of stacked metal layers.

23. The method of claim 22, further comprising forming at least one elongated via disposed in the IC between at least two metal lines among the plurality of stacked metal lines of the source line to couple the at least two metal lines among the plurality of stacked metal lines of the source line together.

24. The method of claim 21, wherein forming the bit line comprising forming the bit line in a plurality of stacked metal layers in the IC disposed above the semiconductor layer.

25. The method of claim 24, wherein forming the bit line comprises forming a plurality of stacked metal lines disposed in the plurality of stacked metal layers electrically coupled together.

26. The method of claim 25, further comprising forming at least one elongated via disposed in the IC between at least two metal lines among the plurality of stacked metal lines of the bit line to electrically couple the at least two metal lines among the plurality of stacked metal lines of the bit line together.

27. The method of claim 21, wherein forming the bit line comprises forming at least one MRAM dedicated metal layer disposed in the IC above the semiconductor layer coupled to the second end electrode of the MTJ.

28. The method of claim 21, further comprising forming a plurality of the MRAM bit cells in the IC;

and

wherein forming the bit line comprises forming a shared bit line coupled between the second end electrode of the MTJs of the plurality of MRAM bit cells.

29. An integrated circuit (IC) comprising at least one magnetic random access memory (MRAM) bit cell, the at least one MRAM bit cell, comprising:

an access transistor disposed in a semiconductor layer of the IC, the access transistor comprising a gate, a source, and a drain;

a magnetic tunnel junction (MTJ) disposed in a metal layer in the IC disposed above the semiconductor layer, the MTJ comprising a first end electrode and a second end electrode;

a drain-side connection column disposed in at least one metal layer in the IC above the semiconductor layer coupling the drain of the access transistor to the first end electrode of the MTJ;

a source line disposed in at least one metal layers in the IC above the semiconductor layer and coupled to the source of the access transistor; and

a bit line disposed in a plurality of stacked metal layers in the IC above the semiconductor layer coupled to the second end electrode of the MTJ.

30. The IC of claim 29, wherein the bit line comprises a plurality of stacked metal lines disposed in the plurality of stacked metal layers and electrically coupled together.

31. The IC of claim 30, wherein at least two metal lines among the plurality of stacked metal lines of the bit line have different lengths from each other.

32. The IC of claim 30, wherein at least two metal lines among the plurality of stacked metal lines of the bit line have different widths from each other.

33. The IC of claim 30, wherein at least two metal lines among the plurality of stacked metal lines of the bit line have different lengths and widths from each other.

34. The IC of claim 30, further comprising at least one elongated via disposed in the IC between at least two metal lines among the plurality of stacked metal lines of the bit line, the at least one elongated via electrically coupling the at least two metal lines among the plurality of stacked metal lines of the bit line together.

35. The IC of claim 29, further comprising at least one MRAM dedicated metal layer disposed in the IC, wherein the bit line is disposed in the at least one MRAM dedicated metal layer.

36. The IC of claim 29, wherein:

the at least one MRAM bit cell comprises a plurality of MRAM bit cells; and

the bit line is comprised of a shared bit line coupled between the first end electrode of the MTJs of the plurality of MRAM bit cells and the drain of each access transistor of the plurality of MRAM bit cells.

37. The IC of claim 29, wherein the MTJ further comprises:

a tunnel barrier between the first end electrode and the second end electrode;

a free layer between the second end electrode and the tunnel barrier; and

a pinned layer between the first end electrode and the tunnel barrier.

38. The IC of claim 29, further comprising a word line disposed in the IC, wherein the word line is coupled to the gate of the access transistor.

39. The IC of claim 29, wherein the at least one MRAM bit cell is comprised of at least one 1T-1MTJ MRAM bit cell.

40. The IC of claim 29, wherein the at least one MRAM bit cell is comprised of at least one 2T-1MTJ MRAM bit cell.

41. The IC of claim 29, wherein the at least one MRAM bit cell is comprised of at least one 2T-2MTJ MRAM bit cell.

42. The IC of claim 29, wherein the at least one MRAM bit cell comprises a plurality of MRAM bit cells in an MRAM array.

43. The IC of claim 42, wherein the MRAM array is disposed in a processor-based memory system of a central processing unit (CPU)-based system.

44. The IC of claim 42 integrated into a system-on-a-chip (SoC).

45. The IC of claim 29 integrated into a device selected from the group consisting of:

a set top box;

an entertainment unit;

a navigation device;

a communications device;

a fixed location data unit;

a mobile location data unit;

a mobile phone;

a cellular phone;

a computer;

a portable computer;

a desktop computer;

a personal digital assistant (PDA);

a monitor;

a computer monitor;

a television;

a tuner;

a radio;

a satellite radio;

a music player;

a digital music player;

a portable music player;

a digital video player;

a video player;

a digital video disc (DVD) player; and

a portable digital video player.

46. A method of fabricating a magnetic random access memory (MRAM) bit cell in an integrated circuit (IC), comprising:

forming an access transistor in a semiconductor layer, the access transistor comprising a gate, a source, and a drain;

forming a magnetic tunnel junction (MTJ) in a metal layer disposed above the semiconductor layer, the MTJ comprising a first end electrode and a second end electrode;

forming a drain-side connection column in at least one metal layer in the IC above the semiconductor layer coupling the drain of the access transistor to the first end electrode of the MTJ;

forming a source line in at least one metal layer above the semiconductor layer coupled to the source of the access transistor; and

forming a bit line in a plurality of stacked metal layers in the IC above the semiconductor layer coupled to the second end electrode of the MTJ.

47. The method of claim 46, wherein forming the bit line comprises forming the bit line in a plurality of stacked metal lines electrically coupled together in the plurality of stacked metal layers.

48. The method of claim 47, further comprising forming at least one elongated via disposed in the IC between at least two metal lines among the plurality of stacked metal lines of the bit line to couple the at least two metal lines among the plurality of stacked metal lines of the bit line together.

49. The method of claim 46, further comprising forming a plurality of the MRAM bit cells in the IC;

and

wherein forming the bit line comprises forming a shared bit line in the plurality of stacked metal layers in the IC above the semiconductor layer, the shared bit line coupled to the second end electrode of the plurality of MRAM bit cells.