LOW COST AND MASK REDUCTION METHOD FOR HIGH VOLTAGE DEVICES

• US 20160254347A1
• Filed: 02/27/2015
• Published: 09/01/2016
• Est. Priority Date: 09/20/2011
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Tsuchiko, Hideaki, Lui, Sik
• Granted Patent: US 9,793,153 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/1008 of lateral transistors
• CPC Class Codes: H01L 29/1058 with PN junction gate
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/6625 Lateral transistors H01L29/66242 and H01L29/66265 take precedence
• CPC Class Codes: H01L 29/66272 Silicon vertical transistors H01L29/66242, H01L29/66257 and H01L29/66265 take precedence
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 29/735 Lateral transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/808 : with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence

Abstract

Aspects of the present disclosure provides a device comprising a P-type semiconductor substrate, an N-type tub above the semiconductor substrate, a P-type region provided in the N-type tub isolated by one or more P-type isolation structures, and an N-type punch-through stopper provided under the P-type regions isolated by the isolation structure(s). The punch-through stopper is heavily doped compared to the N-type tub. The P-type region has a width between the two isolation structures that is equal to or less than that of the N-type punch-through stopper.

Claims

1. A device, comprising:

a semiconductor substrate of a first conductivity type;

a first layer of a second conductivity type provided above the semiconductor substrate of the first conductivity type;

one or more isolation structures of the first conductivity type provided in a portion of the first layer of the second conductivity type, wherein the one or more isolation structures are configured to isolate a region of the first conductivity type formed in the first layer of the second conductivity type, wherein the one or more isolation structures extend in depth through the first layer of the second conductivity type and to the semiconductor substrate of the first conductivity type; and

a punch-through stopper of the second conductivity type provided under the region of the first conductivity type isolated by the one or more isolation structures of the first conductivity type;

wherein the punch-through stopper of the second conductivity type is heavily doped compared to the first layer of the second conductivity type and wherein the region of the first conductivity type has a width that is equal to or less than that of the punch-through stopper of the second conductivity type,

wherein the device is configured as a double diffused metal-oxide-semiconductor (DMOS) device.

3. The device of claim 1, wherein the device is configured as an N-channel lateral double diffused metal-oxide-semiconductor (NLDMOS) device, a double resurf NLDMOS device, or a P-channel LDMOS (PLDMOS) device.

4. The device of claim 1, wherein the first conductivity type is P and the second conductivity type is N.

5. The device of claim 1, wherein the first layer of the second conductivity type has a doping concentration of about 1×

10¹⁵ cm<sup>−

3</sup>.

2. (canceled)

6. The device of claim 6, wherein the punch-through stopper of the second conductivity type has a doping concentration ranging from about 1×

10¹⁶ cm<sup>−

3</sup> to about 1×

10¹⁷ cm³⁻

.

7. A method, comprising:

a) forming an unpatterned first layer of a second conductivity type above a semiconductor substrate of a first conductivity type;

b) forming one or more isolation structures of the first conductivity type, wherein the one or more isolation structures extend in depth through the first layer of the second conductivity type and to the semiconductor substrate of the first conductivity type;

c) forming a region of the first conductivity type with a first well mask in a portion of the first layer that is isolated by the one or more isolation structures, and after forming the region of the first conductivity type, increasing a size of openings of the first well mask; and

then

d) forming a punch-through stopper of the second conductivity type under the region of the first conductivity type that is isolated by the one or more isolation structures, wherein the punch-through stopper of the second conductivity type is heavily doped compared to the first layer of the second conductivity type.

8. The method of claim 7, wherein the first conductivity type is P and the second conductivity type is N.

9. The method of claim 7, wherein the first layer of the second conductivity type has a doping concentration of about 1×

10¹⁵ cm<sup>−

3</sup>.

10. The method of claim 7, wherein the punch-through stopper of the second conductivity type has a doping concentration ranging from about 1×

10¹⁶ cm<sup>−

3</sup> to about 1×

10¹⁷ cm<sup>−

3</sup>.

11. The method of claim 7, wherein the plurality of the isolation structures are formed by ion implantation with an isolation mask followed by a drive-in diffusion process, wherein the isolation mask is aligned with a plurality of active area patterns formed by an active area mask.

12. The method of claim 11, wherein the drive-in diffusion process drives in both ions in the first layer of the second conductivity type and in the isolation structures of the first conductivity type.

13. The method of claim 7, wherein the region of the first conductivity type is formed by performing a medium energy ion implant with a first well mask and the punch-through stopper of the second conductivity type is formed by a high energy ion implant with the first well mask or a second well mask different from the first well mask, wherein the region of the first conductivity type has a width between the two adjacent isolation structures that is equal to or less than that of the punch-through stopper of the second conductivity type.

15. The method of claim 7, wherein the unpatterned first layer of the second conductivity type is formed by blanket implantation.

16. The method of claim 7, wherein the unpatterned first layer of the second conductivity type and the punch-through stopper of the second conductivity type are epitaxial layers formed by deposition, wherein the first layer of the second conductivity type is provided above the punch-through stopper of the second conductivity type.

17. The method of claim 16, further comprising forming a second layer of the second conductivity type under the punch-through stopper of the second conductivity type and above the semiconductor substrate, wherein the second layer of the second conductivity type in an epitaxial layer with a doping concentration similar to that of the first layer of the second conductivity type.

18. The method of claim 16, wherein the punch-through stopper of the second conductivity type is of a thickness that is less than that of the first layer of the second conductivity type.

14. (canceled)

19. A device, comprising:

a P-type semiconductor substrate;

an N-type first layer provided above the P-type semiconductor substrate;

one or more P-type isolation structures provided in a portion of the N-type first layer of the second conductivity type, wherein the one or more isolation structures are configured to isolate a P-type well region formed in the N-type first layer, wherein the one or more isolation structures extend in depth through the N-type first layer and to the P-type semiconductor substrate; and

an N-type punch-through stopper provided under the P-type well region isolated by the one or more P-type isolation structures;

wherein the N-type punch-through stopper is heavily doped compared to the N-type first layer and wherein the P-type well region has a width that is equal to or less than that of the N-type punch-through stopper,

wherein the device is configured as an N-type junction gate field-effect transistor (NJFET) having a highly doped P+ region disposed in the P-type well region provided as a gate.