LOW COST AND MASK REDUCTION METHOD FOR HIGH VOLTAGE DEVICES
First Claim
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1. A device, comprising:
- a semiconductor substrate of a first conductivity type;
a first layer of a second conductivity type provided above the semiconductor substrate of the first conductivity type;
one or more isolation structures of the first conductivity type provided in a portion of the first layer of the second conductivity type, wherein the one or more isolation structures are configured to isolate a region of the first conductivity type formed in the first layer of the second conductivity type, wherein the one or more isolation structures extend in depth through the first layer of the second conductivity type and to the semiconductor substrate of the first conductivity type; and
a punch-through stopper of the second conductivity type provided under the region of the first conductivity type isolated by the one or more isolation structures of the first conductivity type;
wherein the punch-through stopper of the second conductivity type is heavily doped compared to the first layer of the second conductivity type and wherein the region of the first conductivity type has a width that is equal to or less than that of the punch-through stopper of the second conductivity type,wherein the device is configured as a double diffused metal-oxide-semiconductor (DMOS) device.
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Abstract
Aspects of the present disclosure provides a device comprising a P-type semiconductor substrate, an N-type tub above the semiconductor substrate, a P-type region provided in the N-type tub isolated by one or more P-type isolation structures, and an N-type punch-through stopper provided under the P-type regions isolated by the isolation structure(s). The punch-through stopper is heavily doped compared to the N-type tub. The P-type region has a width between the two isolation structures that is equal to or less than that of the N-type punch-through stopper.
9 Citations
19 Claims
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1. A device, comprising:
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a semiconductor substrate of a first conductivity type; a first layer of a second conductivity type provided above the semiconductor substrate of the first conductivity type; one or more isolation structures of the first conductivity type provided in a portion of the first layer of the second conductivity type, wherein the one or more isolation structures are configured to isolate a region of the first conductivity type formed in the first layer of the second conductivity type, wherein the one or more isolation structures extend in depth through the first layer of the second conductivity type and to the semiconductor substrate of the first conductivity type; and a punch-through stopper of the second conductivity type provided under the region of the first conductivity type isolated by the one or more isolation structures of the first conductivity type;
wherein the punch-through stopper of the second conductivity type is heavily doped compared to the first layer of the second conductivity type and wherein the region of the first conductivity type has a width that is equal to or less than that of the punch-through stopper of the second conductivity type,wherein the device is configured as a double diffused metal-oxide-semiconductor (DMOS) device. - View Dependent Claims (3, 4, 5)
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2. (canceled)
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6. The device of claim 6, wherein the punch-through stopper of the second conductivity type has a doping concentration ranging from about 1×
- 1016 cm−
3 to about 1×
1017 cm3−
.
- 1016 cm−
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7. A method, comprising:
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a) forming an unpatterned first layer of a second conductivity type above a semiconductor substrate of a first conductivity type; b) forming one or more isolation structures of the first conductivity type, wherein the one or more isolation structures extend in depth through the first layer of the second conductivity type and to the semiconductor substrate of the first conductivity type; c) forming a region of the first conductivity type with a first well mask in a portion of the first layer that is isolated by the one or more isolation structures, and after forming the region of the first conductivity type, increasing a size of openings of the first well mask; and
thend) forming a punch-through stopper of the second conductivity type under the region of the first conductivity type that is isolated by the one or more isolation structures, wherein the punch-through stopper of the second conductivity type is heavily doped compared to the first layer of the second conductivity type. - View Dependent Claims (8, 9, 10, 11, 12, 13, 15, 16, 17, 18)
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14. (canceled)
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19. A device, comprising:
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a P-type semiconductor substrate; an N-type first layer provided above the P-type semiconductor substrate; one or more P-type isolation structures provided in a portion of the N-type first layer of the second conductivity type, wherein the one or more isolation structures are configured to isolate a P-type well region formed in the N-type first layer, wherein the one or more isolation structures extend in depth through the N-type first layer and to the P-type semiconductor substrate; and an N-type punch-through stopper provided under the P-type well region isolated by the one or more P-type isolation structures;
wherein the N-type punch-through stopper is heavily doped compared to the N-type first layer and wherein the P-type well region has a width that is equal to or less than that of the N-type punch-through stopper,wherein the device is configured as an N-type junction gate field-effect transistor (NJFET) having a highly doped P+ region disposed in the P-type well region provided as a gate.
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Specification