GALLIUM NITRIDE POWER DEVICES

• US 20160254363A1
• Filed: 05/09/2016
• Published: 09/01/2016
• Est. Priority Date: 09/17/2007
• Status: Abandoned Application

• Current Assignee: Transphorm Technology, Inc. (Kohlberg Kravis Roberts & Company LP)
• Original Assignee: Transphorm, Inc (Kohlberg Kravis Roberts & Company LP)
• Inventors: Suh, Chang Soo, Mishra, Umesh
• Application Number:
  US15/149,467
• Publication Number:
  US 20160254363A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/1075 of field-effect transistors
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/432 Heterojunction gate for field effect devices
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/7781 with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
• CPC Class Codes: H01L 29/7783 using III-V semiconductor material
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.

Claims

1. A method of forming a III-nitride device, comprising:

forming a GaN material on a substrate;

forming a passivation layer over the GaN material, wherein the substrate, the GaN material, and the passivation layer are part of a structure having a first side adjacent the substrate and a second side opposite the substrate;

attaching a carrier wafer to the second side of the structure via a bonding layer provided therebetween; and

after attaching the carrier wafer to the second side of the structure, removing the substrate to expose a surface of the GaN material.

2. The method of claim 1, wherein the GaN material comprises a GaN channel layer and an Al_xGaN layer.

3. The method of claim 2, wherein the Al_xGaN layer has a thickness of less than 500 Angstroms.

4. The method of claim 2, wherein the channel layer has a thickness of less than 300 Angstroms.

5. The method of claim 2, wherein the GaN material further comprises a buffer layer between the substrate and the channel layer.

6. The method of claim 5, wherein the buffer layer further comprises a sacrificial layer and an etch stop layer.

7. The method of claim 6, wherein after removing the substrate, the sacrificial layer is selectively removed to expose a planar GaN surface.

8. The method of claim 1, wherein the exposed planar GaN surface is an N-face of the GaN material.

9. The method of claim 1, wherein III-nitride device is an enhancement mode transistor device.

10. The method of claim 1, wherein the III-nitride device is configured to block at least 600V.

20. The method of claim 10, wherein the III-nitride device is configured to block at least 600V.

11. A method of forming a III-nitride device, comprising:

providing, on a substrate, a structure comprising a GaN material and a passivation layer formed on the GaN material, the GaN material contacting the substrate;

attaching a carrier wafer to a side of the structure opposite the substrate, wherein a bonding layer attaches the carrier wafer to the structure; and

after attaching the carrier wafer to the structure, removing the substrate to expose a surface of the GaN material.

12. The method of claim 11, wherein the GaN material comprises a GaN channel layer and an Al_xGaN layer.

13. The method of claim 12, wherein the Al_xGaN layer has a thickness of less than 500 Angstroms.

14. The method of claim 12, wherein the channel layer has a thickness of less than 300 Angstroms.

15. The method of claim 12, wherein the GaN material further comprises a buffer layer between the substrate and the channel layer.

16. The method of claim 15, wherein the buffer layer further comprises a sacrificial layer and an etch stop layer.

17. The method of claim 16, wherein after removing the substrate, the sacrificial layer is selectively removed to expose a planar GaN surface.

18. The method of claim 11, wherein the exposed planar GaN surface is an N-face GaN material.

19. The method of claim 11, wherein the III-nitride device is an enhancement mode transistor device.