RETRIEVAL HASH INDEX

• US 20160259730A1
• Filed: 05/18/2016
• Published: 09/08/2016
• Est. Priority Date: 08/15/2013
• Status: Active Grant

• Current Assignee: Ampere Computing LLC
• Original Assignee: Applied Micro Circuits Corporation (MACOM Technology Solutions Holdings, Inc.)
• Inventors: Svendsen, Kjeld
• Granted Patent: US 9,558,123 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and methods are provided that facilitate retrieval of a hash index in an electronic device. The system contains an addressing component that generates a hash index as a function of an exclusive-or identity. The addressing component can retrieve the hash index as a function of a tag value. Accordingly, required storage area can be reduced and electronic devices can be more efficient.

Claims

1. A device for managing cache memory addressing, comprising:

a controller that receives an address comprising tag data and index data;

a hash component that generates hashed tag data as a function of the tag data and a hashing function;

an identity component that generates identity data as a function of using the hashed tag data as a first operand and the index data as a second operand to an exclusive or operator; and

a memory component that stores the identity data.

2. The device of claim 1, wherein in response to generating the identity data, the index data is discarded.

3. The device of claim 1, wherein the exclusive or operator is a bit wise exclusive or operator.

4. The device of claim 1, wherein in response to receiving a eviction command comprising the address, the hash component generates the hashed tag data as a function of the tag data and the hashing function,

5. The device of claim 4, wherein the controller evicts content from the memory component as a function of an application of the exclusive or operator to the identity data and the hashed tag data.

6. The device of claim 1, wherein the identity data is stored to the memory component in association with the tag data.

7. The device of claim 1, wherein the tag data is compressed as a function of the hash function and the tag data to generate compressed tag data.

8. A method of managing cache addressing, comprising:

receiving, by a system comprising a processor, address data representing a tag and an index;

creating, by the system, a hashed tag as a function of the tag and a defined hash function;

as a function of an exclusive or operator, the hashed tag, and the index creating, by the system, identity data; and

storing, by the system, the identity data to a tag memory.

9. The method of claim 8, further comprising in response to storing the identity data, discarding, by the system, the index.

10. The method of claim 8, wherein the exclusive or operator is a bit wise exclusive or operator.

11. The method of claim 8, further comprising in response to receiving a eviction command comprising at least the tag, creating, by the system, the hashed tag as a function of the tag and the defined hash function,

12. The method of claim 8, wherein the tag represents a first memory location and the index represents a second memory location.

13. The method of claim 8, wherein the identity data is stored to the tag memory in association with the tag.

14. The method of claim 8, further comprising generating a compressed tag by applying the defined hash function to the tag.

15. A computer system, comprising

a processor;

and

a memory for storing executable instructions, that when executed by the processor, perform operations, comprising;

in response to receiving a command comprising tag data and index data, generating a hashed tag as based on the tag data and a hash function;

generating identity data based on an application of a bit wise exclusive or operator using the hashed tag and the index data and a first operand and a second operand; and

storing the identity data to a memory.

16. The computer system of claim 15, further comprising discarding the index data in response to generating the identity data.

17. The computer system of claim 15, wherein the command is one of a write command, a read command, or an eviction command.

18. The computer system of claim 15, wherein the tag data represents a first memory location and the index data represents a second memory location.

19. The computer system of claim 15, further comprising associating the identity data with the tag data in response to storing the identity data to the memory.

20. The computer system of claim 15, further comprising in response to generating the identity data, compressing the tag data as a function of applying the hash function to the tag data to form compressed tag data.