NONVOLATILE MEMORY DEVICE, STORAGE DEVICE HAVING THE SAME, AND OPERATION METHOD THEREOF

• US 20160260489A1
• Filed: 01/21/2016
• Published: 09/08/2016
• Est. Priority Date: 03/02/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Cheon A.N. Lee, Jiho Cho, Ji-Young Lee, Mu-Hui Park, Yoon-Hee Choi
• Inventors: LEE, CHEON AN, CHO, JIHO, PARK, MU-HUI, LEE, JI-YOUNG, CHOI, YOON-HEE
• Granted Patent: US 9,805,807 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

A method of operating a nonvolatile memory device is provided as follows. The nonvolatile memory device includes memory blocks each of which has word lines. A setup voltage is applied to the word lines. A word line voltage is applied to a first word line selected from the word lines. Recovery voltages are applied to the word lines. Each recovery voltage is applied to at least one corresponding word line of the word lines. The recovery voltages have different voltage levels from each other.

Claims

1. A method of operating a nonvolatile memory device including a plurality of memory blocks, each memory block having a plurality of word lines, the method comprising:

applying a setup voltage to the word lines;

applying a word line voltage to a first word line selected from the word lines; and

applying a plurality of recovery voltages to the word lines,

wherein each recovery voltage is applied to at least one corresponding word line of the word lines, and

wherein the recovery voltages have different voltage levels from each other.

2. The method of claim 1,

wherein the setup voltage is a pass voltage in a program operation.

3. The method of claim 2,

wherein the word line voltage is a program voltage in the program operation.

4. The method of claim 1,

wherein in a read operation, the setup voltage includes a word line setup voltage and a read pass voltage, the word line setup voltage being applied to the first word line and the read pass voltage being applied to the other of the word lines, and

wherein the read pass voltage is higher than the word line setup voltage.

5. The method of claim 4,

wherein the word line voltage comprises a read voltage.

6. The method of claim 5,

wherein the read voltage includes a first read voltage and a second read voltage higher than the first read voltage, and

wherein the applying of the word line voltage includes:

applying the first read voltage as the word line voltage to the first word line; and

after the applying of the first read voltage, applying the second read voltage as the word line voltage to the first word line.

7. The method of claim 1,

wherein the voltage levels of the recovery voltages are varied according to a temperature or a program/erase cycle.

8. A method of operating a nonvolatile memory device, the method comprising:

receiving an operation request;

selecting a first memory block from a plurality of memory blocks in response to the operation request; and

applying a plurality of bias voltages to a second memory block,

wherein the first memory block and the second memory block share a first block word line.

9. The method of claim 8, further comprising:

floating a plurality of word lines disposed in a third memory block associated with a second block word line different from the first block word line.

10. The method of claim 8, further comprising:

applying a selection word line voltage and a non-selection word line voltage to an selected word line and non-selection word lines of the first memory block, respectively.

11. The method of claim 10,

wherein the applying of the selection word line voltage and the non-selection word line voltage, if the operation request is a program operation, comprises:

applying a program voltage as the selection word line voltage to the selected word line for a first time;

applying a pass voltage as the non-selection word line voltage to non-selection word lines; and

applying, immediately after elapse of the first time, a plurality of recovery voltages having different voltage levels to the word lines of the first memory block.

12. The method of claim 10,

wherein the applying of the selection word line voltage and the non-selection word line voltage, if the operation request is a read operation or a read verify operation, comprises:

applying a read voltage as the selection word line voltage to the selected word line for a first time;

applying a read pass voltage as the non-selection word line voltage to the non-selection word lines; and

applying, immediately after elapse of the first time, a plurality of recovery voltages to the word lines of the first memory block.

13. The method of claim 8,

wherein voltage levels of the bias voltages are varied according to a temperature or a program/erase cycle.

14. The method of claim 8,

wherein each of the bias voltages is applied to a corresponding zone of a plurality of zones in the second block,

wherein each zone includes at least one word line, and

wherein the bias voltages are different from each other.

15. A storage apparatus comprising:

a non-volatile memory device having a plurality of memory blocks, each memory block having a plurality of word lines; and

a memory controller configured to control the non-volatile memory device, and

wherein the non-volatile memory device comprises;

first and second blocks sharing word lines; and

a control logic controlling,

wherein if the first block is selected and the second block is unselected and if a first word line of the first block is selected, the control logic biases first word line regions of word lines of an unselected memory block of the first and second memory blocks with a plurality of bias voltages having different voltage levels, respectively, and

wherein, during the operation of the selected memory block, the control logic applies a plurality of recovery voltages to a plurality of second word line regions, respectively, and

wherein the word lines of the first memory block is grouped into the plurality of the first recovery voltages.

16. A nonvolatile memory device, comprising:

a plurality of memory blocks including a first memory block and a second memory block, wherein the first memory block and the second memory block are activated at the same time using a block address and wherein each of the plurality of memory blocks includes a plurality of word lines;

a source line driver, in response to a row address,

applying a selection word line voltage to a first word line selected from the word lines of the first memory block and a non-selection word line voltage to the other word lines of the first memory block and

applying a bias voltage to the second memory block.

17. The nonvolatile memory device of claim 16,

wherein the source line driver includes a first source line driver and a second source line driver,

wherein the first source line driver, in response to the row address having the block address, applies the selection word line voltage and the non-selection word line voltage to the first memory block, and

wherein the second source line driver, in response to the row address, applies the bias voltage to the second memory block.

18. The nonvolatile memory device of claim 17,

wherein the first source line driver, after applying the selection word line voltage, further applies each of a plurality of recovery voltages to a corresponding recovery zone of a plurality of recovery zones of the first memory block, and

wherein each recovery zone includes at least one word line of the first memory block.

19. The nonvolatile memory device of claim 18,

wherein a number of the recovery voltages is equal to a number of the recovery zones, and

wherein the recovery voltages are different from each other.

20. The nonvolatile memory device of claim 17, further comprising:

a temperature sensor generating a temperature enable signal; and

a voltage generator, in response to the temperature enable signal, generating the selection word line voltage, the non-selection word line and the bias voltage.