MANUFACTURE METHOD OF TFT SUBSTRATE AND STURCTURE THEREOF
First Claim
1. A manufacture method of an oxide semiconductor TFT substrate, comprising steps of:
- step 1, providing a substrate, and sequentially deposing and patterning a first heavily doped transparent conducting thin film layer and a first metal layer on the substrate to form a gate and the first heavily doped transparent conducting thin film layer located at a lower surface of the gate with the same shape of the gate;
step 2, deposing a gate isolation layer on the gate and the substrate;
step 3, deposing and patterning an oxide semiconductor layer on the gate isolation layer to form an island shaped oxide semiconductor layer directly over the gate;
step 4, deposing and patterning an etching stopper layer on the island shaped oxide semiconductor layer and the gate isolation layer to form an island shaped etching stopper layer on the island shaped oxide semiconductor layer;
a width of the island shaped etching stopper layer is smaller than a width of the island shaped oxide semiconductor layer;
the island shaped etching stopper layer covers a central part of the island shaped oxide semiconductor layer and exposes two side parts of the island shaped oxide semiconductor layer;
step 5, sequentially deposing and patterning a second heavily doped transparent conducting thin film layer, a second metal layer and a third heavily doped transparent conducting thin film layer on the island shaped etching stopper layer and the gate isolation layer to form a source/a drain, the second heavily doped transparent conducting thin film layer located at a lower surface of the source/the drain with the same shape of the source/the drain and the third heavily doped transparent conducting thin film layer located at an upper surface of the source/the drain with the same shape of the source/the drain;
the source/the drain contact the two side parts of the island shaped oxide semiconductor layer via the second heavily doped transparent conducting thin film layer to establish electrical connections;
step 6, deposing and patterning a protecting layer on the third heavily doped transparent conducting thin film layer and the etching stopper layer to form a via located at one side of the island shaped oxide semiconductor layer;
step 7, deposing and patterning a pixel electrode layer on the protecting layer;
the pixel electrode layer fills the via and contacts the source/the drain via the third heavily doped transparent conducting thin film layer to establish electrical connections;
step 8, implementing anneal process to the substrate obtained in the seventh step.
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Abstract
The present invention provides a manufacture method of an oxide semiconductor TFT substrate, and the method comprises steps of: 1, forming a gate (3) and a first heavily doped transparent conducting thin film layer (2) on a substrate (1); 2, deposing a gate isolation layer (4); 3, forming an island shaped oxide semiconductor layer (5); 4, forming an island shaped photoresistor layer (6); 5, forming a source/a drain (8), and a second, a third heavily doped transparent conducting thin film layer (7, 9), and the source/the drain (8) contact the two side parts (53) of the island shaped oxide semiconductor layer (5) via the second heavily doped transparent conducting thin film layer (7) to establish electrical connections; 6, deposing and patterning a protecting layer (10); 7, deposing and patterning a pixel electrode layer (11) which contacts the source/the drain (8) via the third heavily doped transparent conducting thin film layer (9) to establish electrical connections; 8, implementing anneal process.
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Citations
11 Claims
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1. A manufacture method of an oxide semiconductor TFT substrate, comprising steps of:
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step 1, providing a substrate, and sequentially deposing and patterning a first heavily doped transparent conducting thin film layer and a first metal layer on the substrate to form a gate and the first heavily doped transparent conducting thin film layer located at a lower surface of the gate with the same shape of the gate; step 2, deposing a gate isolation layer on the gate and the substrate; step 3, deposing and patterning an oxide semiconductor layer on the gate isolation layer to form an island shaped oxide semiconductor layer directly over the gate; step 4, deposing and patterning an etching stopper layer on the island shaped oxide semiconductor layer and the gate isolation layer to form an island shaped etching stopper layer on the island shaped oxide semiconductor layer; a width of the island shaped etching stopper layer is smaller than a width of the island shaped oxide semiconductor layer;
the island shaped etching stopper layer covers a central part of the island shaped oxide semiconductor layer and exposes two side parts of the island shaped oxide semiconductor layer;step 5, sequentially deposing and patterning a second heavily doped transparent conducting thin film layer, a second metal layer and a third heavily doped transparent conducting thin film layer on the island shaped etching stopper layer and the gate isolation layer to form a source/a drain, the second heavily doped transparent conducting thin film layer located at a lower surface of the source/the drain with the same shape of the source/the drain and the third heavily doped transparent conducting thin film layer located at an upper surface of the source/the drain with the same shape of the source/the drain; the source/the drain contact the two side parts of the island shaped oxide semiconductor layer via the second heavily doped transparent conducting thin film layer to establish electrical connections; step 6, deposing and patterning a protecting layer on the third heavily doped transparent conducting thin film layer and the etching stopper layer to form a via located at one side of the island shaped oxide semiconductor layer; step 7, deposing and patterning a pixel electrode layer on the protecting layer; the pixel electrode layer fills the via and contacts the source/the drain via the third heavily doped transparent conducting thin film layer to establish electrical connections; step 8, implementing anneal process to the substrate obtained in the seventh step. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An oxide semiconductor TFT substrate structure, comprising a substrate, a gate on the substrate, a first heavily doped transparent conducting thin film layer at a lower surface of the gate with the same shape of the gate, a gate isolation layer on the gate and the substrate, an island shaped oxide semiconductor layer directly over the gate on the gate isolation layer, an island shaped etching stopper layer on the island shaped oxide semiconductor layer, a source/a drain on the island shaped etching stopper layer and the gate isolation layer, a third heavily doped transparent conducting thin film layer at a lower surface of the source/the drain with the same shape of the source/the drain, a third heavily doped transparent conducting thin film layer located at an upper surface of the source/the drain with the same shape of the source/the drain, a protecting layer on the third heavily doped transparent conducting thin film layer and the etching stopper layer and a pixel electrode layer on the protecting layer;
- the island shaped oxide semiconductor layer comprises a central part and two side parts;
a width of the island shaped etching stopper layer is smaller than a width of the oxide semiconductor layer and only a central part is covered;
the source/the drain contact the two side parts via the second heavily doped transparent conducting thin film layer to establish electrical connections;
the protecting layer comprises a via located at one side of the island shaped oxide semiconductor layer, and the pixel electrode layer fills the via and contacts the source/the drain via the third heavily doped transparent conducting thin film layer to establish electrical connections. - View Dependent Claims (10)
- the island shaped oxide semiconductor layer comprises a central part and two side parts;
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11. An oxide semiconductor TFT substrate structure, comprising a substrate, a gate on the substrate, a first heavily doped transparent conducting thin film layer at a lower surface of the gate with the same shape of the gate, a gate isolation layer on the gate and the substrate, an island shaped oxide semiconductor layer directly over the gate on the gate isolation layer, an island shaped etching stopper layer on the island shaped oxide semiconductor layer, a source/a drain on the island shaped etching stopper layer and the gate isolation layer, a third heavily doped transparent conducting thin film layer at a lower surface of the source/the drain with the same shape of the source/the drain, a third heavily doped transparent conducting thin film layer located at an upper surface of the source/the drain with the same shape of the source/the drain, a protecting layer on the third heavily doped transparent conducting thin film layer and the etching stopper layer and a pixel electrode layer on the protecting layer;
- the island shaped oxide semiconductor layer comprises a central part and two side parts;
a width of the island shaped etching stopper layer is smaller than a width of the oxide semiconductor layer and only a central part is covered;
the source/the drain contact the two side parts via the second heavily doped transparent conducting thin film layer to establish electrical connections;
the protecting layer comprises a via located at one side of the island shaped oxide semiconductor layer, and the pixel electrode layer fills the via and contacts the source/the drain via the third heavily doped transparent conducting thin film layer to establish electrical connections;wherein material of the source/the drain is copper, material of the first heavily doped transparent conducting thin film layer, and the second heavily doped transparent conducting thin film layer and the third heavily doped transparent conducting thin film layer is heavily doped ITO or heavily doped IZO;
the island shaped oxide semiconductor layer is an IGZO semiconductor layer, and material of the protecting layer is SiO2 or SiON, and material of the pixel electrode layer is ITO or IZO;
thicknesses of the first heavily doped transparent conducting thin film layer, the second heavily doped transparent conducting thin film layer and the third heavily doped transparent conducting thin film layer are respectively in a range of 5-200 nm.
- the island shaped oxide semiconductor layer comprises a central part and two side parts;
Specification