MANUFACTURE METHOD OF TFT SUBSTRATE AND STURCTURE THEREOF

• US 20160260746A1
• Filed: 09/11/2014
• Published: 09/08/2016
• Est. Priority Date: 08/21/2014
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: WANG, Jun
• Granted Patent: US 9,899,421 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The present invention provides a manufacture method of an oxide semiconductor TFT substrate, and the method comprises steps of: 1, forming a gate (3) and a first heavily doped transparent conducting thin film layer (2) on a substrate (1); 2, deposing a gate isolation layer (4); 3, forming an island shaped oxide semiconductor layer (5); 4, forming an island shaped photoresistor layer (6); 5, forming a source/a drain (8), and a second, a third heavily doped transparent conducting thin film layer (7, 9), and the source/the drain (8) contact the two side parts (53) of the island shaped oxide semiconductor layer (5) via the second heavily doped transparent conducting thin film layer (7) to establish electrical connections; 6, deposing and patterning a protecting layer (10); 7, deposing and patterning a pixel electrode layer (11) which contacts the source/the drain (8) via the third heavily doped transparent conducting thin film layer (9) to establish electrical connections; 8, implementing anneal process.

Claims

1. A manufacture method of an oxide semiconductor TFT substrate, comprising steps of:

step 1, providing a substrate, and sequentially deposing and patterning a first heavily doped transparent conducting thin film layer and a first metal layer on the substrate to form a gate and the first heavily doped transparent conducting thin film layer located at a lower surface of the gate with the same shape of the gate;

step 2, deposing a gate isolation layer on the gate and the substrate;

step 3, deposing and patterning an oxide semiconductor layer on the gate isolation layer to form an island shaped oxide semiconductor layer directly over the gate;

step 4, deposing and patterning an etching stopper layer on the island shaped oxide semiconductor layer and the gate isolation layer to form an island shaped etching stopper layer on the island shaped oxide semiconductor layer;

a width of the island shaped etching stopper layer is smaller than a width of the island shaped oxide semiconductor layer;

the island shaped etching stopper layer covers a central part of the island shaped oxide semiconductor layer and exposes two side parts of the island shaped oxide semiconductor layer;

step 5, sequentially deposing and patterning a second heavily doped transparent conducting thin film layer, a second metal layer and a third heavily doped transparent conducting thin film layer on the island shaped etching stopper layer and the gate isolation layer to form a source/a drain, the second heavily doped transparent conducting thin film layer located at a lower surface of the source/the drain with the same shape of the source/the drain and the third heavily doped transparent conducting thin film layer located at an upper surface of the source/the drain with the same shape of the source/the drain;

the source/the drain contact the two side parts of the island shaped oxide semiconductor layer via the second heavily doped transparent conducting thin film layer to establish electrical connections;

step 6, deposing and patterning a protecting layer on the third heavily doped transparent conducting thin film layer and the etching stopper layer to form a via located at one side of the island shaped oxide semiconductor layer;

step 7, deposing and patterning a pixel electrode layer on the protecting layer;

the pixel electrode layer fills the via and contacts the source/the drain via the third heavily doped transparent conducting thin film layer to establish electrical connections;

step 8, implementing anneal process to the substrate obtained in the seventh step.

2. The manufacture method of the oxide semiconductor TFT substrate according to claim 1, wherein material of the source/the drain is copper and material of the pixel electrode layer is ITO or IZO.

3. The manufacture method of the oxide semiconductor TFT substrate according to claim 1, wherein material of the first heavily doped transparent conducting thin film layer, the second heavily doped transparent conducting thin film layer and the third heavily doped transparent conducting thin film layer is heavily doped ITO or heavily doped IZO.

4. The manufacture method of the oxide semiconductor TFT substrate according to claim 3, wherein thicknesses of the first heavily doped transparent conducting thin film layer, the second heavily doped transparent conducting thin film layer and the third heavily doped transparent conducting thin film layer are respectively in a range of 5-200 nm.

5. The manufacture method of the TFT substrate according to claim 4, wherein the thickness of the first heavily doped transparent conducting thin film layer is 10 nm, and the thickness of the second heavily doped transparent conducting thin film layer is 15 nm, and the thickness of the third heavily doped transparent conducting thin film layer is 10 nm.

6. The manufacture method of the oxide semiconductor TFT substrate according to claim 1, wherein the island shaped oxide semiconductor layer is an IGZO semiconductor layer.

7. The manufacture method of the oxide semiconductor TFT substrate according to claim 1, wherein material of the protecting layer is SiO₂ or SiON.

8. The manufacture method of the oxide semiconductor TFT substrate according to claim 1, wherein operations of the patterning are accomplished by photolithography process and etching process.

9. An oxide semiconductor TFT substrate structure, comprising a substrate, a gate on the substrate, a first heavily doped transparent conducting thin film layer at a lower surface of the gate with the same shape of the gate, a gate isolation layer on the gate and the substrate, an island shaped oxide semiconductor layer directly over the gate on the gate isolation layer, an island shaped etching stopper layer on the island shaped oxide semiconductor layer, a source/a drain on the island shaped etching stopper layer and the gate isolation layer, a third heavily doped transparent conducting thin film layer at a lower surface of the source/the drain with the same shape of the source/the drain, a third heavily doped transparent conducting thin film layer located at an upper surface of the source/the drain with the same shape of the source/the drain, a protecting layer on the third heavily doped transparent conducting thin film layer and the etching stopper layer and a pixel electrode layer on the protecting layer;

the island shaped oxide semiconductor layer comprises a central part and two side parts;

a width of the island shaped etching stopper layer is smaller than a width of the oxide semiconductor layer and only a central part is covered;

the source/the drain contact the two side parts via the second heavily doped transparent conducting thin film layer to establish electrical connections;

the protecting layer comprises a via located at one side of the island shaped oxide semiconductor layer, and the pixel electrode layer fills the via and contacts the source/the drain via the third heavily doped transparent conducting thin film layer to establish electrical connections.

10. The TFT substrate structure according to claim 9, wherein material of the source/the drain is copper, material of the first heavily doped transparent conducting thin film layer, and the second heavily doped transparent conducting thin film layer and the third heavily doped transparent conducting thin film layer is heavily doped ITO or heavily doped IZO;

the island shaped oxide semiconductor layer is an IGZO semiconductor layer, and material of the protecting layer is SiO₂ or SiON, and material of the pixel electrode layer is ITO or IZO;

thicknesses of the first heavily doped transparent conducting thin film layer, the second heavily doped transparent conducting thin film layer and the third heavily doped transparent conducting thin film layer are respectively in a range of 5-200 nm.

11. An oxide semiconductor TFT substrate structure, comprising a substrate, a gate on the substrate, a first heavily doped transparent conducting thin film layer at a lower surface of the gate with the same shape of the gate, a gate isolation layer on the gate and the substrate, an island shaped oxide semiconductor layer directly over the gate on the gate isolation layer, an island shaped etching stopper layer on the island shaped oxide semiconductor layer, a source/a drain on the island shaped etching stopper layer and the gate isolation layer, a third heavily doped transparent conducting thin film layer at a lower surface of the source/the drain with the same shape of the source/the drain, a third heavily doped transparent conducting thin film layer located at an upper surface of the source/the drain with the same shape of the source/the drain, a protecting layer on the third heavily doped transparent conducting thin film layer and the etching stopper layer and a pixel electrode layer on the protecting layer;

the island shaped oxide semiconductor layer comprises a central part and two side parts;

a width of the island shaped etching stopper layer is smaller than a width of the oxide semiconductor layer and only a central part is covered;

the source/the drain contact the two side parts via the second heavily doped transparent conducting thin film layer to establish electrical connections;

the protecting layer comprises a via located at one side of the island shaped oxide semiconductor layer, and the pixel electrode layer fills the via and contacts the source/the drain via the third heavily doped transparent conducting thin film layer to establish electrical connections;

wherein material of the source/the drain is copper, material of the first heavily doped transparent conducting thin film layer, and the second heavily doped transparent conducting thin film layer and the third heavily doped transparent conducting thin film layer is heavily doped ITO or heavily doped IZO;

the island shaped oxide semiconductor layer is an IGZO semiconductor layer, and material of the protecting layer is SiO₂ or SiON, and material of the pixel electrode layer is ITO or IZO;

thicknesses of the first heavily doped transparent conducting thin film layer, the second heavily doped transparent conducting thin film layer and the third heavily doped transparent conducting thin film layer are respectively in a range of 5-200 nm.