SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME AND POWER CONVERTER

• US 20160260832A1
• Filed: 03/02/2016
• Published: 09/08/2016
• Est. Priority Date: 03/06/2015
• Status: Abandoned Application

• Current Assignee: Toyoda Gosei Company Limited (Toyota Motor Corporation)
• Original Assignee: Toyoda Gosei Company Limited (Toyota Motor Corporation)
• Inventors: OKA, Tohru, INA, Tsutomu
• Application Number:
  US15/059,195
• Publication Number:
  US 20160260832A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H02M 1/4225 using a non-isolated boost converter
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

An object is to effectively reduce electric field crowding in a trench MIS structure in a semiconductor device. The semiconductor device comprises a first semiconductor layer; a second semiconductor layer; a third semiconductor layer; a trench that is configured to include a side face and a bottom face; a first insulator that is mainly made of a first insulating material, is provided as a film formed from the side face over the bottom face and is configured to include a side face film portion and a bottom face film portion; a second insulator that is mainly made of a second insulating material having a higher relative permittivity than relative permittivity of the first insulating material and is formed in at least a corner portion of an area defined by the side face film portion and the bottom face film portion; and an electrode that is formed inside of the trench via the first insulator and the second insulator. A thickness Th1 of the second insulator in an area located in the corner portion, relative to a surface of the bottom face film portion is greater than a thickness Th2 of the second insulator in an area where the side face film portion is placed between the second insulator and the second semiconductor layer, relative to a surface of the side face film portion.

Claims

1. A semiconductor device, comprising:

a first semiconductor layer that is configured to have one characteristic out of n-type and p-type characteristics;

a second semiconductor layer that is configured to have the other characteristic out of the n-type and p-type characteristics that is different from the one characteristic, and is stacked on the first semiconductor layer;

a third semiconductor layer that is configured to have the one characteristic and is stacked on the second semiconductor layer;

a trench that is formed from the third semiconductor layer to penetrate through the second semiconductor layer and to be recessed into the first semiconductor layer and is configured to include a side face and a bottom face;

a first insulator that is mainly made of a first insulating material, is provided as a film formed from the side face over the bottom face, and is configured to include a side face film portion formed on the side face and a bottom face film portion formed on the bottom face;

a second insulator that is mainly made of a second insulating material having a higher relative permittivity than relative permittivity of the first insulating material and is formed in at least a corner portion of an area defined by the side face film portion and the bottom face film portion; and

an electrode that is formed inside of the trench via the first insulator and the second insulator, wherein

a thickness Th1 of the second insulator in an area located in the corner portion is greater than a thickness Th2 of the second insulator in an area where the side face film portion is placed between the second insulator and the second semiconductor layer, wherein

the thickness Th1 denotes a thickness relative to a surface of the bottom face film portion and

the thickness Th2 denotes a thickness relative to a surface of the side face film portion.

2. The semiconductor device according to claim 1, wherein

the thickness Th1 is greater than a thickness of the first insulator.

3. The semiconductor device according to claim 1, wherein

the bottom face film portion has a thickness that is equal to or greater than a thickness of the side face film portion.

4. The semiconductor device according to claim 1, wherein

the thickness Th1 is equal to or greater than twice a thickness of the bottom face film portion.

5. The semiconductor device according to claim 1, wherein

an interface between the second insulator and the electrode is located on a third semiconductor layer side of an interface between the first semiconductor layer and the second semiconductor layer.

6. The semiconductor device according to claim 1, wherein

the second insulator is a film formed from the side face film portion over the bottom face film portion.

7. The semiconductor device according to claim 1, wherein

the second insulator includes

a film portion that is formed on the side face film portion to have the thickness Th2 and

a film portion that is formed on the bottom face film portion to have the thickness Th1.

8. The semiconductor device according to claim 1, wherein

the second insulator is formed partly thicker in the corner portion.

9. The semiconductor device according to claim 1, wherein

the second insulator is partly formed in the corner portion.

10. The semiconductor device according to claim 1, wherein

the first insulating material includes at least one selected from the group consisting of silicon dioxide (SiO₂), silicon oxynitride (SiON), aluminum oxide (Al₂O₃), aluminum oxynitride (AlON) and gallium oxide (Ga₂O₃).

11. The semiconductor device according to claim 1, wherein

the second insulating material includes at least one of oxides and oxynitrides containing at least one element selected from the group consisting of aluminum (Al), hafnium (Hf), titanium (Ti), zirconium (Zr), tantalum (Ta) and lanthanum (La).

12. The semiconductor device according to claim 1, wherein

at least one semiconductor layer among the first semiconductor layer, the second semiconductor layer and the third semiconductor layer is mainly made of a semiconductor that has a greater band gap than a band gap of silicon (Si).

13. The semiconductor device according to claim 1, wherein

at least one semiconductor layer among the first semiconductor layer, the second semiconductor layer and the third semiconductor layer is mainly made of at least one selected from the group consisting of silicon carbide (SiC), a nitride semiconductor, diamond and gallium oxide (Ga₂O₃).

14. A power converter, comprising

the semiconductor device according to claim 1.

15. A method of manufacturing a semiconductor device, the method comprising:

forming a first semiconductor layer having one characteristic out of n-type and p-type characteristics, on a substrate;

stacking a second semiconductor layer having the other characteristic out of the n-type and p-type characteristics that is different from the one characteristic, on the first semiconductor layer;

stacking a third semiconductor layer having the one characteristic, on the second semiconductor layer;

forming a trench that includes a side face and a bottom face by etching from the third semiconductor layer through the second semiconductor layer to the first semiconductor layer;

forming a first insulator as a film formed from the side face over the bottom face by using a first insulating material, such that the first insulator includes a side face film portion formed on the side face and a bottom face film portion formed on the bottom face;

forming a second insulator in at least a corner portion of an area defined by the side face film portion and the bottom face film portion by using a second insulating material having a higher relatively permittivity than relative permittivity of the first insulating material; and

forming an electrode inside of the trench that the first insulator and the second insulator are formed in, wherein

the forming the second insulator comprises making a thickness Th1 of the second insulator in an area located in the corner portion greater than a thickness Th2 of the second insulator in an area where the side face film portion is placed between the second insulator and the second semiconductor layer, wherein

the thickness Th1 denotes a thickness relative to a surface of the bottom face film portion and

the thickness Th2 denotes a thickness relative to a surface of the side face film portion.

16. The method of manufacturing the semiconductor device according to claim 15,

wherein the forming the second insulator comprises forming the second insulator by sputtering.

17. The method of manufacturing the semiconductor device according to claim 16,

wherein the sputtering is electron cyclotron resonance sputtering.

18. The method of manufacturing the semiconductor device according to claim 17, the method further comprising

adjusting thickness of the second insulator by controlling an angle between a radiation direction of target particles and the substrate.