SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

• US 20160260838A1
• Filed: 03/03/2016
• Published: 09/08/2016
• Est. Priority Date: 03/06/2015
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei
• Granted Patent: US 10,727,355 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device includes first and second insulators over a substrate, a semiconductor over the second insulator, first and second conductors over the semiconductor, a third insulator over the semiconductor, a fourth insulator over the third insulator, a third conductor over the fourth insulator, and a fifth insulator over the first insulator, the first conductor and the second conductor. The semiconductor includes first, second, and third regions. The first region overlaps with the third conductor with the third insulator and the fourth insulator positioned therebetween. The second region overlaps with the third conductor with the first conductor, the fourth insulator, and the fifth insulator positioned therebetween. The third region overlaps with the third conductor with the second conductor, the fourth insulator, and the fifth insulator positioned therebetween. The fourth insulator is in contact with a side surface of the fifth insulator in a region overlapping with the semiconductor.

Claims

1. A semiconductor device comprising:

a first insulator over a substrate;

a second insulator over the first insulator;

a semiconductor over the second insulator;

a first conductor and a second conductor over the semiconductor;

a third insulator over the semiconductor;

a fourth insulator over the third insulator;

a third conductor over the fourth insulator; and

a fifth insulator over the first insulator, the first conductor and the second conductor,

wherein the semiconductor includes a first region, a second region, and a third region,

wherein the first region is overlapped with the third conductor with the third insulator and the fourth insulator positioned therebetween,

wherein the second region is overlapped with the third conductor with the first conductor, the fourth insulator, and the fifth insulator positioned therebetween,

wherein the third region is overlapped with the third conductor with the second conductor, the fourth insulator, and the fifth insulator positioned therebetween, and

wherein the fourth insulator includes a region in contact with a side surface of the fifth insulator.

2. The semiconductor device according to claim 1, wherein the third insulator has a stacked-layer structure including a plurality of layers.

3. The semiconductor device according to claim 1, wherein the semiconductor includes a CAAC-OS.

4. The semiconductor device according to claim 1, wherein each of the first to third conductors has a stacked-layer structure including a plurality of layers.

5. The semiconductor device according to claim 1, wherein each of the first conductor and the second conductor includes regions with different thicknesses.

6. The semiconductor device according to claim 1, further comprising a fourth conductor under the first insulator.

7. The semiconductor device according to claim 1, wherein each of the second insulator and the third insulator contains at least one element contained in the semiconductor other than oxygen.

8. The semiconductor device according to claim 1, wherein a top surface of the third insulator is over top surfaces of the first conductor and the second conductor in a cross-sectional shape.

9. A method for manufacturing a semiconductor device, comprising:

forming a first insulator;

forming a second insulator over the first insulator;

forming a semiconductor over the second insulator;

forming a multilayer film including the second insulator and the semiconductor by etching a part of the second insulator and a part of the semiconductor;

forming a first conductor over the multilayer film;

forming a second conductor and a third conductor by etching a part of first conductor;

forming a fourth conductor over the second conductor and the third conductor;

forming a third insulator over the fourth conductor and the first insulator;

dividing the fourth conductor into a fifth conductor and a sixth conductor by forming an opening, through which the semiconductor and the first insulator are exposed, in the third insulator and the fourth conductor;

forming a fourth insulator over the third insulator, the fifth conductor, the sixth conductor, and the semiconductor;

forming a fifth insulator by selectively etching a part of the fourth insulator so that a region in contact with the semiconductor is left and a part of a side surface of the third insulator is exposed;

forming a sixth insulator over the fifth insulator and the third insulator; and

forming a seventh conductor over the sixth insulator,

wherein each of the second insulator and the fourth insulator contains at least one element contained in the semiconductor other than oxygen.

10. The method for manufacturing the semiconductor device according to claim 9, wherein each of the first and the seventh conductors has a stacked-layer structure including a plurality of layers.

11. The method for manufacturing the semiconductor device according to claim 9, wherein the first insulator is formed over a conductor.

12. The method for manufacturing the semiconductor device according to claim 9, wherein a top surface of the fifth insulator is over top surfaces of the fifth conductor and the sixth conductor in a cross-sectional shape.

13. The method for manufacturing the semiconductor device according to claim 9, wherein each of the second conductor and the third conductor includes regions with different thicknesses.

14. The method for manufacturing the semiconductor device according to claim 9, wherein a crystallinity of the part of the fourth insulator to be selectively etched is lower than a crystallinity of the fifth insulator.

15. The method for manufacturing the semiconductor device according to claim 9, wherein the etching for the part of the fourth insulator is performed by wet etching using an acid solution.

16. The method for manufacturing the semiconductor device according to claim 9, wherein the fourth insulator has a stacked-layer structure including a plurality of layers.

17. A method for manufacturing a semiconductor device, comprising:

forming a first insulator;

forming a second insulator over the first insulator;

forming a semiconductor over the second insulator;

forming a first conductor over the semiconductor;

forming a multilayer film including the second insulator, the semiconductor, and the first conductor by etching a part of the second insulator, a part of the semiconductor, and a part of the first conductor;

forming a third insulator over the multilayer film;

dividing the first conductor into a second conductor and a third conductor by forming an opening, through which the semiconductor is exposed, in the third insulator and the first conductor;

forming a fourth insulator over the third insulator, the second conductor, the third conductor, and the semiconductor;

forming a fifth insulator by selectively etching a part of the fourth insulator so that a region in contact with the semiconductor is left and a part of a side surface of the third insulator is exposed;

forming a sixth insulator over the fifth insulator and the third insulator; and

forming a fourth conductor over the sixth insulator,

wherein each of the second insulator and the fourth insulator contains at least one element contained in the semiconductor other than oxygen.

18. The method for manufacturing the semiconductor device according to claim 17, wherein each of the first and the fourth conductors has a stacked-layer structure including a plurality of layers.

19. The method for manufacturing the semiconductor device according to claim 17, wherein the first insulator is formed over a conductor.

20. The method for manufacturing the semiconductor device according to claim 17, wherein a top surface of the fifth insulator is over top surfaces of the second conductor and the third conductor in a cross-sectional shape.

21. The method for manufacturing the semiconductor device according to claim 17, wherein each of the second conductor and the third conductor includes regions with different thicknesses.

22. The method for manufacturing the semiconductor device according to claim 17, wherein a crystallinity of the part of the fourth insulator to be selectively etched is lower than a crystallinity of the fifth insulator.

23. The method for manufacturing the semiconductor device according to claim 17, wherein the etching for the part of the fourth insulator is performed by wet etching using an acid solution.

24. The method for manufacturing the semiconductor device according to claim 17, wherein the fourth insulator has a stacked-layer structure including a plurality of layers.