RF Circuit with Switch Transistor with Body Connection

• US 20160261265A1
• Filed: 04/23/2015
• Published: 09/08/2016
• Est. Priority Date: 03/06/2015
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm Switch Corp. (Qualcomm, Inc.)
• Inventors: Aubain, Max Samuel, Kemerling, Clint
• Granted Patent: US 9,900,001 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/30 Modifications for providing a predetermined threshold before switching shaping pulses by thresholding H03K5/08
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET
• CPC Class Codes: H03K 3/01 Details

Abstract

In some method and apparatus embodiments, an RF circuit comprises a switch transistor having a source, a drain, a gate, and a body. A gate control voltage is applied to the gate of the switch transistor. A body control voltage is applied to the body of the switch transistor. The body control voltage is a positive bias voltage when the switch transistor is in an on state. In some embodiments, an RF circuit comprises a control voltage applied to the gate of the switch transistor through a first resistance and applied to the body of the switch transistor through a second resistance. The first resistance is different from the second resistance.

Claims

1. An RF circuit comprising:

an N-channel switch transistor having a source, a drain, a gate, and a body;

a gate control voltage applied to the gate of the switch transistor; and

a body control voltage applied to the body of the switch transistor, wherein the body control voltage is a positive bias voltage when the switch transistor is in an on state.

2. The RF circuit of claim 1, further comprising:

a first voltage control source that produces the gate control voltage; and

a second voltage control source that produces the body control voltage, wherein the second voltage control source is different from the first voltage control source.

3. The RF circuit of claim 2, wherein:

the first voltage control source is a first level shifter; and

the second voltage control source is a second level shifter.

4. The RF circuit of claim 1, further comprising:

a voltage control source that produces the gate control voltage and the body control voltage as a single control voltage that is applied through a first resistance to the gate of the switch transistor and through a second resistance to the body of the switch transistor;

wherein the first resistance is different from the second resistance; and

wherein the first resistance and the second resistance share a common circuit node.

6. The RF circuit of claim 1, wherein:

the positive bias voltage when the switch transistor is in the on state is greater than about 0.7 volts.

7. The RF circuit of claim 1, wherein:

the positive bias voltage improves device linearity of the RF circuit when the switch transistor is in the on state.

8. The RF circuit of claim 7, wherein:

the improved device linearity is a mitigated harmonic signal.

9. The RF circuit of claim 8, wherein:

the harmonic signal is at three times a fundamental frequency of the RF circuit.

10. The RF circuit of claim 7, wherein:

the improved device linearity is a mitigated intermodulation distortion.

5. (canceled)

11. An RF circuit comprising:

all an N-channel switch transistor having a source, a drain, a gate, and a body; and

a control voltage applied to the gate of the switch transistor through a first resistance and applied to the body of the switch transistor through a second resistance, wherein the first resistance is different from the second resistance and wherein the control voltage is configured to apply a positive bias to the body when the control voltage turns the switch transistor on.

12. The RF circuit of claim 11, wherein:

the control voltage applied through the second resistance is a bias voltage that is greater than about 0.7 volts when the switch transistor is in an on state.

13. The RF circuit of claim 11, wherein:

the control voltage applied through the second resistance improves device linearity of the RF circuit when the switch transistor is in an on state.

14. The RF circuit of claim 13, wherein:

the improved device linearity is a mitigated harmonic signal at three times a fundamental frequency of the RF circuit.

15. A method comprising:

in a switching circuit, passing an electrical signal from a first node to a second node through a first switch during an on state of the first switch, wherein the first switch includes a plurality of N-channel transistors coupling the first node to the second node, each of the transistors having a source, a drain, a gate, and a body;

during the on state of the first switch, applying a gate control voltage to respective gates of the transistors; and

during the on state of the first switch, applying a positive control bias to the respective bodies of the transistors.

16. The method of claim 15, wherein the electrical signal comprises a Radio Frequency (RF) carrier signal.

17. The method of claim 15, further comprising:

applying a negative control bias to the respective bodies of the transistors during an off state of the first switch.

18. The method of claim 15, further comprising:

decoding control signals to produce decoded signals;

passing the decoded signals to a level shifter;

generating a control voltage at the level shifter based on the decoded signals;

generating the gate control voltage and the positive control bias from the control voltage.

19. The method of claim 15, further comprising:

further comprising;

producing the gate control voltage and the positive control bias as a single control voltage that is applied through a first resistance to the gates of the transistors and through a second resistance to the bodies of the transistors, wherein the first resistance is different from the second resistance; and

wherein the first resistance and the second resistance share a common circuit node.

20. The method of claim 15, wherein the plurality of transistors are coupled source to drain from the first node to ground.