TRANSMITTER AND SHORTENING METHOD THEREOF

• US 20160261374A1
• Filed: 04/15/2016
• Published: 09/08/2016
• Est. Priority Date: 03/02/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, Kyung-Joong, MYUNG, Se-ho, JEONG, Hong-sil
• Granted Patent: US 10,277,251 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: H03M 13/1148 Structural properties of the code parity-check or generator matrix
• CPC Class Codes: H03M 13/1157 Low-density generator matrices [LDGM]
• CPC Class Codes: H03M 13/1165 QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
• CPC Class Codes: H03M 13/1191 Codes on graphs other than LDPC codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/253 with concatenated codes
• CPC Class Codes: H03M 13/255 with Low Density Parity Check [LDPC] codes
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/611 Specific encoding aspects, e.g. encoding by means of decoding
• CPC Class Codes: H03M 13/618 Shortening and extension of codes
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0063 Single parity check
• CPC Class Codes: H04L 1/0069 Puncturing patterns

Abstract

A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to constitute Low Density Parity Check (LDPC) information bits including the outer-encoded bits and zero bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the LDPC information bits are divided into a plurality of bit groups, and wherein the zero padder pads zero bits to at least some of the plurality of bit groups, each of which is formed of a same number of bits, to constitute the LDPC information bits based on a predetermined shortening pattern which provides that the some of the plurality of bit groups are not sequentially disposed in the LDPC information bits.

Claims

1. A transmitter comprising:

a zero padder is configured to pad zero bits to at least part of LDPC information bits;

an LDPC encoder configured to encode the LDPC information bits according to a code rate of 3/15 and a code length of 16200,

wherein the zero padder pads the zero bits to at least part of bit groups among bit groups constituting the LDPC information bits based on pattern described below;

2. The transmitter of claim 1, further comprising:

an outer encoder is configured to encode input bits to generate parity bits, and

wherein the zero padder calculates a number N_pad of bit groups in which all bits among the at least part of bit groups are to be padded by zero bits based on a following equation;

3. The transmitter of claim 2, wherein the zero padder pads zero bits to all the bits of a π

_s(0)-th bit group, a π

_s(1)-th bit group, . . . , a π

_s(N_pad−

1)-th bit group among the bit groups based on the pattern.

4. The transmitter of claim 3, wherein the zero padder additionally pads zero bits to K_ldpc−

N_outer−

360×

N_pad bits from a first bit of a π

_s(N_pad)-th bit group.

5. A shortening method of a transmitter, comprising:

padding zero bits to at least part of LDPC information bits; and

encoding the LDPC information bits according to a code rate of 3/15 and a code length of 16200,

wherein the padding the zero bits pads the zero bits to at least part of bit groups among bit groups constituting the LDPC information bits based on pattern described below;

6. The method of claim 5, further comprising:

outer-encoding input bits to generate parity bits, and

wherein the padding the zero bits calculates a number N_pad of bit groups in which all bits among the at least part of bit groups are to be padded by zero bits based on a following equation;

7. The method of claim 6, wherein the padding the zero bits pads zero bits to all the bits of a π

_s(0)-th bit group, a π

_s(1)-th bit group, . . . , a π

_s(N_pad−

1)-th bit group among the bit groups based on the pattern.

8. The method of claim 7, wherein the padding the zero bits additionally pads zero bits to K_ldpc−

N_outer−

360×

N_pad bits from a first bit of a π

_s(N_pad)-th bit group.