LOW POWER HIGH SPEED RECEIVER WITH REDUCED DECISION FEEDBACK EQUALIZER SAMPLERS
First Claim
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1. An apparatus comprising:
- a Variable Gain Amplifier (VGA);
a set of samplers to sample data output from the VGA according to a clock signal; and
a Clock Data Recovery (CDR) circuit to adjust phase of the clock signal such that magnitude of a first post-cursor signal associated with the sampled data is substantially half of a magnitude of a primary cursor tap associated with the sampled data.
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Abstract
Described is an apparatus which comprises: a Variable Gain Amplifier (VGA); a set of samplers to sample data output from the VGA according to a clock signal; and a Clock Data Recovery (CDR) circuit to adjust phase of the clock signal such that magnitude of a first post-cursor signal associated with the sampled data is substantially half of a magnitude of a primary cursor tap associated with the sampled data.
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20 Claims
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1. An apparatus comprising:
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a Variable Gain Amplifier (VGA); a set of samplers to sample data output from the VGA according to a clock signal; and a Clock Data Recovery (CDR) circuit to adjust phase of the clock signal such that magnitude of a first post-cursor signal associated with the sampled data is substantially half of a magnitude of a primary cursor tap associated with the sampled data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A system comprising:
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a memory; a processor coupled to the memory, the processor having a receiver which comprises; a Variable Gain Amplifier (VGA); a set of samplers to sample data output from the VGA according to a clock signal; and a Clock Data Recovery (CDR) circuit to adjust phase of the clock signal such that magnitude of a first post-cursor signal associated with the sampled data is substantially half of a magnitude of a primary cursor tap associated with the sampled data; and a wireless interface for allowing the processor to communicate with another device. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification