MULTI-BIT FLIP-FLOP REORGANIZATION TECHNIQUES

• US 20160266604A1
• Filed: 03/09/2015
• Published: 09/15/2016
• Est. Priority Date: 03/09/2015
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Krishnamurthy, Harsha, Velayoudame, Muthukumaravelu
• Granted Patent: US 9,513,658 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 1/14 Time supervision arrangements, e.g. real time clock
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/396 Clock trees
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply

Abstract

A process utilized in an integrated circuit design methodology may be used to assess and organize individual bits (e.g., flip-flops) within multi-bit clocked storage devices (e.g., multi-bit flip-flops) for use in the integrated circuit design. The process may include assessing timing slacks of the bits, sorting and/or assigning the bits based on the assessed timing slacks, and remapping the multi-bit clocked storage devices using the sorted and/or assigned bits. One or more timing corrections may be applied to the remapped multi-bit clocked storage devices. The timing corrections may include useful clock skewing or resizing (e.g., upsizing or downsizing) of the remapped multi-bit clocked storage devices.

Claims

1. A method, comprising:

assessing, by one or more processors, one or more timing slack properties of input pins and output pins on each bit in a plurality of multi-bit clocked storage devices utilized in a design for an integrated circuit, wherein the plurality of multi-bit clocked storage devices comprise a common logical clock input;

assigning, by the one or more processors, based on the assessed timing slack properties of the bits, each of the bits to one bit group selected from a plurality of bit groups;

remapping, by the one or more processors, the bits within the plurality of multi-bit clocked storage devices such that at least one of the multi-bit clocked storage devices comprises two or more bits selected from one bit group; and

applying one or more timing corrections to one or more of the multi-bit clocked storage devices, wherein at least one timing correction is applied to the at least one multi-bit clocked storage device that comprises the two or more bits selected from the one bit group.

2. The method of claim 1, wherein the one or more timing slack properties comprise a negative or positive timing slack and a relative magnitude of the timing slack.

3. The method of claim 1, wherein the at least one timing correction comprises clock skewing of the at least one multi-bit clocked storage device.

4. The method of claim 1, wherein the at least one timing correction comprises resizing the at least one multi-bit clocked storage device.

5. The method of claim 1, further comprising sorting, by the one or more processors based on the assessed timing slack properties of the bits, the bits into a selected order determined by at least one of the assessed timing slack properties, and assigning each of the bits to the one bit group selected from the plurality of bit groups.

6. The method of claim 5, wherein the plurality of bit groups is formed by dividing the sorted bits into a plurality of groups.

7. The method of claim 1, wherein at least one bit group selected from the plurality of bit groups comprises at least one common timing slack property among the bits assigned to the bit group.

8. The method of claim 7, wherein the common timing slack property comprises a timing slack property that is the same or is closest to being the same among the assessed timing slack properties of the bits.

9. The method of claim 1, wherein the at least one multi-bit clocked storage device that comprises the two or more bits selected from the one bit group comprises at least one common timing slack property among the two or more bits.

10. The method of claim 1, wherein the multi-bit clocked storage devices comprise at least one of a multi-bit flip-flop, a multi-bit latch, and a multi-bit register.

11. A non-transitory computer accessible storage medium including instructions that, when executed by one or more processors, cause the one or more processors to perform a method, comprising:

assessing one or more timing slack properties of input pins and output pins on individual flip-flops in a plurality of multi-bit flip-flops utilized in a design for an integrated circuit, wherein the plurality of multi-bit flops comprise a common logical clock input;

sorting, based on at least one of the assessed timing slack properties of the individual flip-flops, the individual flip-flops into a selected order;

remapping the individual flip-flops to the plurality of multi-bit flip-flops, wherein the individual flip-flops are remapped to the plurality of multi-bit flip-flops based on the selected order; and

applying one or more timing corrections to one or more of the multi-bit flip-flops, wherein at least one timing correction is applied to at least one of the multi-bit flip-flops that comprises individual flip-flops remapped to the at least one multi-bit flip-flop.

12. The computer accessible storage medium of claim 11, wherein the one or more timing slack properties comprise a negative or positive timing slack and a relative magnitude of the timing slack.

13. The computer accessible storage medium of claim 11, wherein applying the at least one timing correction comprises applying clock skewing to the individual flip-flops remapped to the at least one multi-bit flip-flop.

14. The computer accessible storage medium of claim 11, wherein applying the at least one timing correction comprises resizing the at least one multi-bit flip-flop with the remapped individual flip-flops.

15. The computer accessible storage medium of claim 11, wherein sorting the individual flip-flops into the selected order comprises sorting the individual flip-flops such that adjacent individual flip-flops in the selected order have a related timing slack property.

16. The computer accessible storage medium of claim 15, wherein the related timing slack property comprises a timing slack property that is the same or is closest to being the same among the assessed timing slack properties of the individual flip-flops.

17. The computer accessible storage medium of claim 11, wherein each multi-bit flip-flop that comprises remapped individual flip-flops comprises at least one common timing slack property among the remapped individual flip-flops.

18. The computer accessible storage medium of claim 17, wherein the common timing slack property comprises a timing slack property that is the same or is closest to being the same among the assessed timing slack properties of the individual flip-flops.

19. The computer accessible storage medium of claim 11, wherein the individual flip-flops sorted in the selected order comprise individual flip-flops within a pre-determined placement radius in the design for the integrated circuit.

20. The computer accessible storage medium of claim 11, further comprising providing a load from at least one of the multi-bit flops, wherein the load is divided among the individual flip-flops remapped to the at least one multi-bit flop.