MULTI-CHIP TOUCH ARCHITECTURE FOR SCALABILITY

• US 20160266679A1
• Filed: 01/11/2016
• Published: 09/15/2016
• Est. Priority Date: 03/10/2015
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: PANT, Vivek, SHAHPARNIA, Shahrooz, KRAH, Christoph H.
• Granted Patent: US 10,488,992 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 3/0416 Control or interface arrangements specially adapted for digitisers
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G06F 3/04184 Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
• CPC Class Codes: G06F 3/044 by capacitive means

Abstract

A multi-chip touch architecture for scalability can include one or more touch controller application specific integrated circuits (ASICs), and one or more switching circuits coupled between the one or more touch controller ASICs and the touch sensor panel. The number of touch controller ASICs and switching circuits can be scaled based on the size of the touch sensor panel. The touch controller ASICs can include an interface for data transfer between the touch controller ASICs to allow for parallel processing of an image of touch by more than one touch controller ASIC. The touch controller ASIC can also include a memory directly accessible by more than one processing circuit (e.g., hardware accelerators), and circuitry to dynamically adjust the coupling between portions (e.g., banks) of memory and inputs of the one or more processing circuits to minimize data transfer and improve processing speeds.

Claims

1. An integrated circuit comprising:

a receive section including a plurality of receive channels configured to receive signals from sensing operations;

a memory configured to store data based on the signals from the receive section; and

a plurality of processing circuits, wherein at least two of the plurality of processing circuits are configured to directly access the memory, and one or more of the plurality of processing circuits is configured to process the data stored in the memory.

2. The integrated circuit of claim 1, further comprising a switching unit coupled between the memory and at least one of the plurality of processing circuits, wherein the switching unit is configured to dynamically couple one or more banks of the memory to one or more inputs or one or more outputs of the one or more of the plurality of processing circuits.

3. The integrated circuit of claim 2, wherein the switching unit is coupled between the memory and at least one hardware accelerator, and the switching unit is configured to dynamically couple one or more banks of the memory to one or more inputs or one or more outputs of the at least one hardware accelerator circuit.

4. The integrated circuit of claim 1, wherein the memory includes a plurality of access ports for simultaneous direct access of the memory by one or more of the plurality of processing circuits.

5. The integrated circuit of claim 1, wherein the plurality of processing circuits includes one or more hardware accelerators configured to process the data stored in the memory.

6. The integrated circuit of claim 1, wherein at least one of the plurality of processing circuits is configured to sequence the processing of the data stored in the memory by the one or more of the plurality of processing circuits.

7. The integrated circuit of claim 6, wherein sequencing the processing of the data stored in the memory includes distributing processing of one or more algorithms between the one or more of the plurality of processing circuits.

8. The integrated circuit of claim 5, wherein the one or more hardware accelerators include a first hardware accelerator to perform one or more of scaling the data stored in the memory, subtracting a baseline amount from the data stored in the memory, and adding or subtracting an offset to the data stored in the memory.

9. The integrated circuit of claim 5, wherein the one or more hardware accelerators include a first hardware accelerator to generate a mapping of pixel locations with signals above a first threshold and below a second threshold.

10. The integrated circuit of claim 5, wherein the one or more hardware accelerators include a first hardware accelerator to perform an image diffusion algorithm.

11. The integrated circuit of claim 5, wherein the one or more hardware accelerators include a first hardware accelerator configured to convert data represented by a magnitude component and a phase component into data represented by an in-phase component and a quadrature component, or to convert data represented by the in-phase component and the quadrature component into data represented by the magnitude component and the phase component.

12. The integrated circuit of claim 1, further comprising an interface with one or more ports for transmitting first touch signals to, or receiving second touch signals from, another integrated circuit.

13. The integrated circuit of claim 1, wherein at least one processing circuit of the plurality of processing circuits is configured to generate an image of touch from the signals received by receive section or the data stored in the memory based on one or more parameters associated with the signals or the data, the parameters including one or more of a chip identifier, a scan step, a scan type and a receive channel number.

14. The integrated circuit of claim 13, wherein the at least one processing circuit of the plurality of processing circuits is configured to map information associated with the signals or the data stored in the memory to physical pixel locations in order to generate the image of touch.

15. A method for processing data from sensing scans in an integrated circuit comprising a plurality of sense channels, a storage device, and a plurality of processing circuits, the method comprising:

receiving signals at the plurality of sense channels from the sensing scans;

storing first data based on the signals received at the plurality of sense channels in the storage device; and

simultaneously processing the data in the storage device by the plurality of processing circuits, the data in the storage device including the first data, wherein at least two of the plurality of processing circuits simultaneously access the storage device.

16. The method of claim 15, further comprising:

switching a coupling between data storage locations and one or more inputs or one or more outputs of at least one of the plurality of processing circuits.

17. The method of claim 15, wherein at least one of the plurality of processing circuits is a hardware accelerator configured to process the data.

18. The method of claim 17, wherein the hardware accelerator performs operations including one or more of scaling the data, subtracting a baseline amount from the data, adding or subtracting an offset to the data, generating a mapping of pixel locations with signals above a first threshold or below a second threshold, diffusing an image, and converting between a magnitude and phase representation and an in-phase component and quadrature component representation.

19. The method of claim 15, further comprising:

receiving second data from another integrated circuit; and

storing the second data in the storage device;

wherein the data in the storage device processed by the plurality of processing circuits further includes the second data.

20. The method of claim 19, further comprising:

generating an image of touch from the data in the storage device based on one or more parameters associated with the first data or the second data, the parameters including one or more of a circuit identifier, a scan step, a scan type and a receive channel number.

21. A non-transitory computer readable storage medium having stored thereon instructions, which when executed by a processor, perform a method for processing data from sensing scans in an integrated circuit comprising a plurality of sense channels, a storage device, and a plurality of processing circuits, the method comprising:

receiving signals at the plurality of sense channels from the sensing scans;

storing first data based on the signals received at the plurality of sense channels in the storage device; and

simultaneously processing the data in the storage device by the plurality of processing circuits, the data in the storage device including the first data, wherein at least two of the plurality of processing circuits simultaneously access the storage device.

22. The non-transitory computer readable storage medium of claim 21, further comprising:

switching a coupling between data storage locations and one or more inputs or one or more outputs of at least one of the plurality of processing circuits.

23. The non-transitory computer readable storage medium of claim 21, where at least one of the plurality of processing circuits is a hardware accelerator configured to process the data.

24. The non-transitory computer readable storage medium of claim 21, further comprising:

receiving second data from another integrated circuit; and

storing the second data in the storage device;

wherein the data in the storage device processed by the plurality of processing circuits further includes the second data.

25. The non-transitory computer readable storage medium of claim 24, further comprising:

generating an image of touch from the data in the storage device based on one or more parameters associated with the first data or the second data, the parameters including one or more of a circuit identifier, a scan step, a scan type and a receive channel number.