DIVISION OPERATIONS ON VARIABLE LENGTH ELEMENTS IN MEMORY
First Claim
1. A method for performing division operations comprising:
- performing a division operation on;
a first vector comprising at least two elements that are different in length representing a number of dividends and initially stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array; and
a second vector comprising at least two elements that are different in length representing a number of divisors and initially stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array;
wherein the division operation includes dividing the first vector by the second vector by performing a number of operations and at least one of the number of operations are performed without transferring data via an input/output (I/O) line.
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Accused Products
Abstract
Examples of the present disclosure provide apparatuses and methods for performing variable bit-length division operations in a memory. An example method comprises performing a variable length division operation on a first vector comprising variable length elements representing a number of dividends and stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second vector comprising variable length elements representing a number of divisors stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include dividing the first vector by the second vector by performing a number of operations. The method can include performing at least one of the number of operations without transferring data via an input/output (I/O) line.
140 Citations
40 Claims
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1. A method for performing division operations comprising:
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performing a division operation on; a first vector comprising at least two elements that are different in length representing a number of dividends and initially stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array; and a second vector comprising at least two elements that are different in length representing a number of divisors and initially stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array; wherein the division operation includes dividing the first vector by the second vector by performing a number of operations and at least one of the number of operations are performed without transferring data via an input/output (I/O) line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An apparatus comprising:
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a first group of memory cells in a memory array coupled to a first access line and configured to store a first dividend element; a second group of memory cells coupled to the first access line and configured to store a second dividend element; a third group of memory cells coupled to a second access line and configured to store a first divisor element; a fourth group of memory cells coupled to the second access line and configured to store a second divisor element; and a controller configured to operate sensing circuitry to divide the first dividend element by the first divisor element and to divide the second dividend element by the second divisor element by performing a number of operations, wherein at least one of the number of operations is performed without transferring data via an input/output (I/O) line. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A method for performing a number of division operations on variable length elements, comprising:
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using a controller configured to operate sensing circuitry for performing a division operation on; a first vector comprising at least two elements that are different in length representing a number of dividends and initially stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array; a second vector comprising at least two elements that are different in length representing a number of divisors and initially stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array; wherein the division operation includes dividing the first vector by the second vector by performing a number of operations on pitch with the memory array; and storing a result of the division operation as a third vector stored in a group of memory cells coupled to a third access line. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33)
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34. A method for dividing variable length elements comprising:
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performing a variable length division operation in a memory array on; a plurality (M) of first elements stored in a first group of memory cells coupled to a first access line and to a number of sense lines of a memory array, wherein at least two of the plurality of first elements have different bit-lengths; and a plurality (M) of second elements stored in the second group of memory cells coupled to a second access line and to the number of sense lines of the memory array, wherein at least two of the plurality of second elements have different bit-lengths; and providing a division operation result that indicates a quotient of each corresponding element of the plurality of M first elements with each corresponding element of the plurality of M second elements. - View Dependent Claims (35)
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36. An apparatus, comprising:
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a plurality of memory cells; sensing circuitry comprising a plurality of sense amplifiers each coupled to a corresponding one of the memory cells and a plurality of compute components each coupled to a corresponding one of the sense amplifiers to implement a logic operation, and the sensing circuitry configured to temporarily store elements of at least a dividend bit-vector and a divisor bit-vector that are used to perform a division operation. - View Dependent Claims (37, 38, 39, 40)
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Specification