PROGRAM PROCESSING APPARATUS AND METHOD, AND IMAGE FORMING APPARATUS

• US 20160266933A1
• Filed: 02/18/2016
• Published: 09/15/2016
• Est. Priority Date: 03/09/2015
• Status: Active Grant

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Sakai, Katsuya
• Granted Patent: US 10,324,667 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 3/122 with regard to computing resources, e.g. memory, CPU
• CPC Class Codes: G06F 9/5033 considering data affinity
• CPC Class Codes: G06K 15/1857 involving parallel processing in the same printing apparatus

Abstract

Threads that are generated during specific processing are managed, with an operation core of threads that are generated during activation processing being fixed to a specific core, and an operation core of threads for specific processing that are generated after the activation processing is complete not being set. Also, the setting of the operation core of threads for specific processing that were generated before the timing at which the activation processing is completed is restored to an original setting.

Claims

1. A program processing apparatus that executes a plurality of threads using a multi-core processor that includes a plurality of processor cores and a cache for each of the processor cores, comprising:

a thread management unit configured to store an identifier of a generated thread;

an allocation unit configured to, in a predetermined operation state, fixedly allocate the generated thread of a specific program to a specific processor core; and

a unit configured to, upon detecting that the predetermined operation state has been canceled, release the fixed allocation of the thread having the identifier managed by the thread management unit to the specific processor core.

2. The program processing apparatus according to claim 1, wherein the predetermined operation state is a state in which the same data is cached in the respective caches for the plurality of processor cores.

3. The program processing apparatus according to claim 1,

wherein the specific program is a virtual machine that executes an application program, and

the predetermined operation state is a state from when the specific program starts activation of the application program until when activation of all application programs that are to be activated is complete.

4. The program processing apparatus according to claim 1, wherein the allocation unit, in a case where an operation state is not the predetermined operation state, does not allocate the generated thread to the specific processor core, and processor core allocation for a thread not allocated to the specific processor core is performed by an operating system.

5. The program processing apparatus according to claim 1, wherein the specific processor core is a specific one of the plurality of processor cores.

6. The program processing apparatus according to claim 3, wherein the virtual machine is a Java virtual machine, and the application program is a Java application.

7. An image processing apparatus comprising:

a program processing device configured to execute a plurality of threads using a multi-core processor that includes a plurality of processor cores and a cache for each of the processor cores, the program processing device including;

a thread management unit configured to store an identifier of a generated thread;

an allocation unit configured to, in a predetermined operation state, fixedly allocate the generated thread of a specific program to a specific processor core; and

a unit configured to, upon detecting that the predetermined operation state has been canceled, release the fixed allocation of the thread having the identifier managed by the thread management unit to the specific processor core;

a scanner configured to read an image;

a printer configured to print an image; and

a control unit configured to provide an interface between the scanner, the printer and an application program that is executed by the program processing device.

8. A program processing method for executing a plurality of threads with a multi-core processor that includes a plurality of processor cores and a cache for each of the processor cores, comprising:

storing an identifier of a generated thread;

fixedly allocating, in a predetermined operation state, the generated thread of a specific program to a specific processor core; and

releasing, upon detecting that the predetermined operation state has been canceled, the fixed allocation of the thread having the stored identifier to the specific processor core.

9. A program processing apparatus that executes a plurality of threads using a multi-core processor that includes a plurality of processor cores and a cache for each of the processor cores, comprising:

a generation unit configured to generate a thread of an application program; and

an allocation unit configured to allocate the thread of the application program to one processor core of the plurality of processor cores,

wherein the allocation unit, during activation of the application program, fixedly allocates the thread of the application program to a first processor core, and, after activation of the application program is complete, does not fixedly allocate the thread of the application program to the first processor core.

10. A non-transitory computer-readable medium storing a program for causing a computer that executes a plurality of threads using a multi-core processor that includes a plurality of processor cores and a cache for each of the processor cores to execute a process, the process comprising:

storing an identifier of a generated thread;

fixedly allocating, in a predetermined operation state, the generated thread of a specific program to a specific processor core; and

releasing, upon detecting that the predetermined operation state has been canceled, the fixed allocation of the thread having the stored identifier to the specific processor core.