ULTRATHIN MULTILAYER METAL ALLOY LINER FOR NANO CU INTERCONNECTS
First Claim
1. A process comprising:
- (a) forming wire embedded in a dielectric layer on a semiconductor substrate, said wire comprising a copper core comprising sidewalls and a bottom of said copper core, a top surface of said wire coplanar with a top surface of said dielectric layer;
(b) forming an electrically conductive alloy liner on said sidewalls based on Mn, with at least one of Co and/or W to minimize or eliminate EM and/or TDDB;
(c) without exposing said substrate to oxygen, forming a dielectric liner over said alloy liner, any exposed portions of said alloy liner, and said dielectric layer.
1 Assignment
0 Petitions
Accused Products
Abstract
Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers.
5 Citations
16 Claims
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1. A process comprising:
- (a) forming wire embedded in a dielectric layer on a semiconductor substrate, said wire comprising a copper core comprising sidewalls and a bottom of said copper core, a top surface of said wire coplanar with a top surface of said dielectric layer;
(b) forming an electrically conductive alloy liner on said sidewalls based on Mn, with at least one of Co and/or W to minimize or eliminate EM and/or TDDB;
(c) without exposing said substrate to oxygen, forming a dielectric liner over said alloy liner, any exposed portions of said alloy liner, and said dielectric layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 15)
- (a) forming wire embedded in a dielectric layer on a semiconductor substrate, said wire comprising a copper core comprising sidewalls and a bottom of said copper core, a top surface of said wire coplanar with a top surface of said dielectric layer;
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9-14. -14. (canceled)
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16-20. -20. (canceled)
Specification