SEMICONDUCTOR PACKAGE ASSEMBLY

• US 20160268234A1
• Filed: 02/03/2016
• Published: 09/15/2016
• Est. Priority Date: 03/13/2015
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: PENG, I-Hsuan, LIN, Tzu-Hung, HSIAO, Ching-Wen
• Granted Patent: US 9,711,488 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/32265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73209 Bump and HDI connectors
• CPC Class Codes: H01L 2224/92133 the second connecting process involving a bump connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06558 the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1432 : Central processing unit [CPU]
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/19011 : including integrated passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip

Abstract

The invention provides a semiconductor package assembly. The semiconductor package assembly includes a semiconductor die. A first molding compound covers a back surface of the semiconductor die. A redistribution layer (RDL) structure is disposed on a front surface of the semiconductor die. The semiconductor die is coupled to the RDL structure. A second molding compound is disposed on the front surface of the semiconductor die and embedded in the RDL structure. A passive device is disposed on the second molding compound and coupled to the semiconductor die.

Claims

1. A semiconductor package assembly, comprising:

a semiconductor die;

a first molding compound covering a back surface of the semiconductor die;

a redistribution layer (RDL) structure disposed on a front surface of the semiconductor die, wherein the semiconductor die is coupled to the RDL structure;

a second molding compound disposed on the front surface of the semiconductor die and embedded in the redistribution layer (RDL) structure; and

a passive device disposed on the second molding compound and coupled to the semiconductor die.

2. The semiconductor package assembly as claimed in claim 1, further comprising:

a conductive bump passing through the second molding compound, wherein the passive device is coupled to the semiconductor die through the conductive bump.

3. The semiconductor package assembly as claimed in claim 1, wherein a sidewall of the second molding compound is surrounded by the redistribution layer (RDL) structure.

4. The semiconductor package assembly as claimed in claim 1, wherein the first molding compound is separated from the second molding compound through the semiconductor die and the redistribution layer (RDL) structure.

5. The semiconductor package assembly as claimed in claim 1, wherein the passive device is embedded in the redistribution layer (RDL) structure.

6. The semiconductor package assembly as claimed in claim 1, wherein an interface between the passive device and the second molding compound is aligned to a first surface of the redistribution layer (RDL) structure, which is away from the semiconductor die.

7. The semiconductor package assembly as claimed in claim 6, further comprising:

conductive structures disposed on the first surface of the redistribution layer (RDL) structure, wherein the conductive structures are coupled to the redistribution layer (RDL) structure.

8. The semiconductor package assembly as claimed in claim 6, wherein the redistribution layer (RDL) structure comprises conductive traces extended into the second molding compound.

9. A semiconductor package assembly, comprising:

a semiconductor die;

a first molding compound disposed on a first surface of the semiconductor die;

a redistribution layer (RDL) structure disposed on a second surface opposite the first surface of the semiconductor die;

a second molding compound disposed on the second surface of the semiconductor die and embedded in the redistribution layer (RDL) structure, wherein the second molding compound is separated from the first molding compound through the redistribution layer (RDL) structure; and

a passive device disposed on the second molding compound and coupled to the semiconductor die.

10. The semiconductor package assembly as claimed in claim 9, wherein the redistribution layer (RDL) structure and the second molding compound cover different portions of the second surface of the semiconductor die.

11. The semiconductor package assembly as claimed in claim 9, further

a conductive bump passing through the second molding compound, wherein the passive device is coupled to the semiconductor die through the conductive bump.

12. The semiconductor package assembly as claimed in claim 9, wherein a sidewall of the second molding compound is surrounded by the redistribution layer (RDL) structure.

13. The semiconductor package assembly as claimed in claim 9, wherein the passive device is embedded in the redistribution layer (RDL) structure.

14. The semiconductor package assembly as claimed in claim 9, wherein an interface between the passive device and the second molding compound is aligned to a first surface of the redistribution layer (RDL) structure, which is away from the semiconductor die.

15. The semiconductor package assembly as claimed in claim 14, further comprising:

conductive structures disposed on the first surface of the redistribution layer (RDL) structure, wherein the conductive structures are coupled to the redistribution layer (RDL) structure.

16. The semiconductor package assembly as claimed in claim 14, wherein the redistribution layer (RDL) structure comprises conductive traces extended into the second molding compound.

17. A semiconductor package assembly, comprising:

a semiconductor die;

a first molding compound in contact with a first surface of the semiconductor die;

a redistribution layer (RDL) structure covering a first portion of a second surface opposite the first surface of the semiconductor die;

a second molding compound covering a second portion of the second surface of the semiconductor die and embedded in the RDL structure; and

a passive device covering the second portion of the second surface of the semiconductor die, wherein the second molding compound is disposed between the semiconductor die and the passive device.

18. The semiconductor package assembly as claimed in claim 17, wherein the second molding compound is separated from the first molding compound through the redistribution layer (RDL) structure.

19. The semiconductor package assembly as claimed in claim 17, further comprising:

a conductive bump passing through the second molding compound, wherein the passive device is coupled to the semiconductor die through the conductive bump.

20. The semiconductor package assembly as claimed in claim 17, wherein the passive device is embedded in the redistribution layer (RDL) structure.

21. The semiconductor package assembly as claimed in claim 17, wherein an interface between the passive device and the second molding compound is aligned to a first surface of the redistribution layer (RDL) structure, which is away from the semiconductor die.

22. The semiconductor package assembly as claimed in claim 21, further comprising:

conductive structures disposed on the first surface of the redistribution layer (RDL) structure, wherein the conductive structures are coupled to the redistribution layer (RDL) structure.

23. The semiconductor package assembly as claimed in claim 21, wherein the redistribution layer (RDL) structure comprises conductive traces extended into the second molding compound.