REDUCING RISK OF PUNCH-THROUGH IN FINFET SEMICONDUCTOR STRUCTURE

• US 20160268260A1
• Filed: 02/23/2016
• Published: 09/15/2016
• Est. Priority Date: 03/09/2015
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: LIM, Kwanyong, AKARVARDAR, Murat Kerem
• Granted Patent: US 9,847,333 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence

Abstract

Reducing a chance of punch-through in a FinFET structure includes providing a substrate, creating a blanket layer of semiconductor material with impurities therein over the substrate, masking a portion of the blanket layer, creating epitaxial semiconductor material on an unmasked portion of the structure, removing the mask, and etching the structure to create n-type raised structure(s) and p-type raised structure(s), a bottom portion of the raised structure(s) being surrounded by isolation material. A middle portion of the raised structure(s) includes a semiconductor material with impurities therein, the middle portion extending across the raised structure(s), and a top portion including a semiconductor material lacking added impurities.

Claims

1. A method, comprising:

providing a substrate;

creating a blanket layer of semiconductor material with impurities therein over the substrate;

masking a portion of the blanket layer;

creating epitaxial semiconductor material on an unmasked portion of the structure;

removing the mask; and

etching the structure to create at least one n-type raised structure and at least one p-type raised structure.

2. The method of claim 1, wherein the substrate comprises a bulk semiconductor substrate.

3. The method of claim 1, further comprising creating a blanket top layer of epitaxial semiconductor material lacking impurities after removing the mask and before etching the structure.

4. The method of claim 1, wherein the masked portion comprises one of a n-type region and a p-type region.

5. The method of claim 4, wherein creating the epitaxial semiconductor material comprises creating epitaxial semiconductor material of a type opposite the type of the masked portion.

6. The method of claim 1, wherein the blanket layer comprises epitaxial semiconductor material with impurities therein.

7. The method of claim 6, further comprising creating a blanket layer of epitaxial semiconductor material lacking impurities over the blanket layer of semiconductor material with impurities prior to the masking.

8. The method of claim 7, wherein the structure comprises a n-type region and a p-type region, and wherein the masking comprises masking the n-type region, the method further comprising removing both blanket layers on the p-type region.

9. The method of claim 8, wherein creating the epitaxial semiconductor material on the unmasked portion comprises creating p-type epitaxial semiconductor material on the p-type region, the method further comprising creating a top layer of epitaxial semiconductor material lacking impurities on the p-type region prior to removing the mask.

10. A semiconductor structure, comprising:

a substrate; and

at least one raised semiconductor structure coupled to the substrate, a bottom portion of the at least one raised structure being surrounded by isolation material;

wherein a middle portion of the at least one raised structure comprises a semiconductor material with impurities therein, wherein the middle portion extends across the at least one raised structure, and wherein a top portion comprises a semiconductor material lacking added impurities.

11. The semiconductor structure of claim 10, wherein the semiconductor material with impurities therein comprises epitaxial semiconductor material.

12. The semiconductor structure of claim 11, wherein the structure comprises a n-type region and a p-type region, and wherein the epitaxial semiconductor material with impurities therein comprises boron-doped epitaxial silicon germanium.

13. The semiconductor structure of claim 10, wherein the at least one raised structure comprises a n-type raised structure and a p-type raised structure, wherein the semiconductor structure is silicon-based, and wherein a middle portion of the p-type raised structure comprises phosphorous-doped silicon.

14. The semiconductor structure of claim 13, wherein the phosphorous-doped silicon comprises phosphorous-doped epitaxial silicon.

15. The semiconductor structure of claim 10, wherein the at least one raised structure comprises a n-type raised structure and a p-type raised structure, wherein the semiconductor structure is silicon-based, and wherein a middle portion of the p-type raised structure comprises arsenic-doped silicon.

16. The semiconductor structure of claim 15, wherein the arsenic-doped silicon comprises arsenic-doped epitaxial silicon.

17. The semiconductor structure of claim 10, wherein the at least one raised structure comprises a n-type raised structure and a p-type raised structure, wherein the semiconductor structure is silicon-based, and wherein the top portion of the p-type raised structure comprises epitaxial silicon germanium lacking added impurities.

18. The semiconductor structure of claim 10, further comprising a gate surrounding a top portion of the at least one raised structure.