METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
First Claim
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1. A method of manufacturing a semiconductor device comprising:
- forming, on a semiconductor substrate, a stacked body in which a plurality of films is stacked;
forming a first mask pattern on the stacked body;
forming a second mask pattern on the stacked body;
repeating first processing including processing of etching the stacked body, and processing of slimming the second mask pattern;
forming a first step-like pattern in which a lower side than the second mask pattern is remained, and a first dummy pattern in which a lower side than the first mask pattern is remained, from the stacked body;
removing the second mask pattern when the second mask pattern becomes smaller than a predetermined size;
applying a resist on the semiconductor substrate;
forming a third mask pattern using the resist on the stacked body;
repeating second processing including processing of etching the stacked body, and processing of slimming the third mask pattern; and
forming a second step-like pattern in which a lower side than the first step-like pattern is remained, and a second dummy pattern in which a lower side than the first dummy pattern is remained, from the stacked body.
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Abstract
In a method of manufacturing a semiconductor device of an embodiment, first and second mask patterns are formed on a stacked body formed on a semiconductor substrate. Then, a first step-like pattern and a first dummy pattern are formed from the stacked body. When the second mask pattern becomes smaller than a predetermined size, a resist is applied, and a third mask pattern using the resist is formed. Then, a second step-like pattern and a second dummy pattern are formed from the stacked body.
9 Citations
20 Claims
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1. A method of manufacturing a semiconductor device comprising:
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forming, on a semiconductor substrate, a stacked body in which a plurality of films is stacked; forming a first mask pattern on the stacked body; forming a second mask pattern on the stacked body; repeating first processing including processing of etching the stacked body, and processing of slimming the second mask pattern; forming a first step-like pattern in which a lower side than the second mask pattern is remained, and a first dummy pattern in which a lower side than the first mask pattern is remained, from the stacked body; removing the second mask pattern when the second mask pattern becomes smaller than a predetermined size; applying a resist on the semiconductor substrate; forming a third mask pattern using the resist on the stacked body; repeating second processing including processing of etching the stacked body, and processing of slimming the third mask pattern; and forming a second step-like pattern in which a lower side than the first step-like pattern is remained, and a second dummy pattern in which a lower side than the first dummy pattern is remained, from the stacked body. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A semiconductor device comprising:
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memory cells arranged on a semiconductor substrate in a three-dimensional manner; electrode films formed in a step-like manner and connected to the memory cells; and a dummy pattern having a predetermined height and arranged in a region where the electrode films are not formed. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification
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Current AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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Original AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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InventorsMATSUNAGA, Yosuke, KUNIYA, Takuji
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Application NumberUS14/741,621Publication NumberTime in Patent OfficeDaysField of SearchUS Class Current1/1CPC Class CodesH10B 43/27 the channels comprising ver...H10B 43/50 characterised by the bounda...
