SEMICONDUCTOR DEVICE OR MEMORY DEVICE AND DRIVING METHOD THEREOF

• US 20160268436A1
• Filed: 03/09/2016
• Published: 09/15/2016
• Est. Priority Date: 03/13/2015
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: ASAMI, Yoshinobu
• Granted Patent: US 9,905,700 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 2029/42388 characterised by the shape of the insulating material
• CPC Class Codes: H01L 27/0705 comprising components of the field effect type
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1233 with different thicknesses of the active layer in different devices
• CPC Class Codes: H01L 27/1237 with a different composition, shape, layout or thickness of the gate insulator in different devices
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A highly integrated semiconductor device that holds data and includes a first semiconductor layer, a first gate insulating film over the first semiconductor layer, a first gate electrode over the first gate insulating film, a second semiconductor layer over the first gate electrode, a conductive layer over the second semiconductor layer, a second gate insulating film covering the second semiconductor layer and the conductive layer, and a second gate electrode covering at least part of a side surface of the second semiconductor layer with the second gate insulating film interposed therebetween. An end portion of the second semiconductor layer is substantially aligned with an end portion of the conductive layer.

Claims

1. A semiconductor device comprising:

a first semiconductor layer;

a first gate insulating film over the first semiconductor layer;

a first electrode over the first gate insulating film;

a second semiconductor layer over and in contact with the first electrode;

a conductive layer over the second semiconductor layer;

a second gate insulating film covering the second semiconductor layer and the conductive layer; and

a second electrode covering at least part of a side surface of the second semiconductor layer with the second gate insulating film interposed therebetween,

wherein an end portion of the second semiconductor layer and an end portion of the conductive layer are substantially aligned with each other.

4. The semiconductor device according to claim 1, further comprising:

a pair of electrodes over the first semiconductor layer; and

an interlayer film over the pair of electrodes, the interlayer film comprising an opening portion;

wherein a top surface of the interlayer film, a top surface of the first gate insulating film, and a top surface of the first electrode are substantially aligned with each other, and

wherein the first gate insulating film is in contact with a top surface of the first semiconductor layer in the opening portion.

6. The semiconductor device according to claim 1, wherein the first electrode, the second semiconductor layer, and the conductive layer overlap with each other.

9. The semiconductor device according to claim 1, wherein the first electrode covers the first semiconductor layer in a channel width direction.

12. The semiconductor device according to claim 1, wherein each of the first semiconductor layer and the second semiconductor layer comprises an oxide semiconductor.

15. The semiconductor device according to claim 12, wherein the oxide semiconductor includes a crystal having c-axis alignment.

2. A semiconductor device comprising:

a first transistor comprising;

a first semiconductor layer;

a first gate insulating film over the first semiconductor layer; and

a first electrode over the first gate insulating film; and

a second transistor comprising;

the first electrode;

a second semiconductor layer over and in contact with the first electrode;

a conductive layer over the second semiconductor layer;

a second gate insulating film covering the second semiconductor layer and the conductive layer; and

a second electrode covering at least part of a side surface of the second semiconductor layer with the second gate insulating film interposed therebetween,

wherein an end portion of the second semiconductor layer and an end portion of the conductive layer are substantially aligned with each other.

5. The semiconductor device according to claim 2, further comprising:

a pair of electrodes over the first semiconductor layer; and

an interlayer film over the pair of electrodes, the interlayer film comprising an opening portion;

wherein a top surface of the interlayer film, a top surface of the first gate insulating film, and a top surface of the first electrode are substantially aligned with each other, and

wherein the first gate insulating film is in contact with a top surface of the first semiconductor layer in the opening portion.

7. The semiconductor device according to claim 2, wherein the first electrode, the second semiconductor layer, and the conductive layer overlap with each other.

10. The semiconductor device according to claim 2, wherein the first electrode covers the first semiconductor layer in a channel width direction.

13. The semiconductor device according to claim 2, wherein each of the first semiconductor layer and the second semiconductor layer comprises an oxide semiconductor.

16. The semiconductor device according to claim 13, wherein the oxide semiconductor includes a crystal having c-axis alignment.

3. A semiconductor device comprising:

a first semiconductor layer;

a first gate insulating film over the first semiconductor layer;

a first electrode over the first gate insulating film;

a second semiconductor layer over and in contact with the first electrode;

a conductive layer over the second semiconductor layer;

a second gate insulating film covering the first electrode, the second semiconductor layer, and the conductive layer; and

a second electrode covering at least part of a side surface of the second semiconductor layer with the second gate insulating film interposed therebetween,

wherein an end portion of the first electrode, an end portion of the second semiconductor layer, and an end portion of the conductive layer are substantially aligned with each other.

8. The semiconductor device according to claim 3, wherein the first electrode, the second semiconductor layer, and the conductive layer overlap with each other.

11. The semiconductor device according to claim 3, wherein the first electrode covers the first semiconductor layer in a channel width direction.

14. The semiconductor device according to claim 3, wherein each of the first semiconductor layer and the second semiconductor layer comprises an oxide semiconductor.

17. The semiconductor device according to claim 14, wherein the oxide semiconductor includes a crystal having c-axis alignment.

18. A method of driving a memory device,

the memory device comprising:

a first semiconductor layer;

a first gate insulating film over the first semiconductor layer;

a first electrode over the first gate insulating film;

a second semiconductor layer over and in contact with the first electrode;

a conductive layer over the second semiconductor layer;

a second gate insulating film covering the second semiconductor layer and the conductive layer; and

a second electrode covering at least part of a side surface of the second semiconductor layer with the second gate insulating film interposed therebetween,

wherein the first electrode, the second semiconductor layer, and the conductive layer overlapping with each other, and

the method comprising the steps of;

bringing the conductive layer and the first electrode into electrical contact with each other through the second semiconductor layer, so that data is written into the memory device, and

breaking the electrical contact between the conductive layer and the first electrode and then changing a potential of the conductive layer, so that the data is read by capacitive coupling with the second semiconductor layer as a dielectric between the conductive layer and the first electrode.

19. The method of driving a memory device according to claim 18, wherein the first electrode, the second semiconductor layer, and the conductive layer overlap with each other.

20. The method of driving a memory device according to claim 18, wherein the first electrode covers the first semiconductor layer in a channel width direction.

21. The method of driving a memory device according to claim 18, wherein each of the first semiconductor layer and the second semiconductor layer comprises an oxide semiconductor.

22. The method of driving a memory device according to claim 21, wherein the oxide semiconductor includes a crystal having c-axis alignment.