Buck/Boost Circuit that Charges and Discharges Multi-Cell Batteries of a Power Bank Device

• US 20160268816A1
• Filed: 03/13/2015
• Published: 09/15/2016
• Est. Priority Date: 03/13/2015
• Status: Active Grant

• Current Assignee: Active-Semi, Inc. (Qorvo, Inc.)
• Original Assignee: Active-Semi, Inc. (Qorvo, Inc.)
• Inventors: Mao, Hong
• Granted Patent: US 9,479,004 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H02J 2207/20 Charging or discharging characterised by the power electronics converter
• CPC Class Codes: H02J 7/0013 acting upon several batteries simultaneously or sequentially H02J7/1423 takes precedence
• CPC Class Codes: H02J 7/0063 with circuits adapted for supplying loads from the battery
• CPC Class Codes: H02J 7/0068 Battery or charger load switching, e.g. concurrent charging and load supply H02J7/0013 takes precedence
• CPC Class Codes: H02J 7/007 Regulation of charging or discharging current or voltage

Abstract

A power bank device has a single circuit topology involving a DC-to-DC converter and four transistors so that this single topology can be used both to charge battery cells with a regulated current in a charging step-up boost mode and to drive a regulated voltage onto a power bank voltage output node in a discharging step-down buck mode. In one example, the circuit includes a first transistor coupled to conduct current between a battery voltage node and a switch node SW, a second transistor coupled to conduct current between the SW node and a ground node, and third and fourth transistors coupled in series to conduct current between a voltage input node and the voltage output node. The inductor of the converter is coupled between the SW node and the voltage output node, and the output capacitor of the converter is coupled between the voltage output node and the ground node.

Claims

1. A power bank circuit comprising:

a voltage input (VIN) terminal;

a voltage output (VOUT) terminal;

at least one rechargeable battery, wherein the at least one rechargeable battery has an operating voltage range from a fully uncharged operating voltage VBATL to a fully charged operating voltage VBATH, wherein the operating voltage range is between a ground (GND) node and a battery (VBAT) node;

a first field effect transistor S1 coupled to switch current between the VBAT node and a switch (SW) node;

a second field effect transistor S2 coupled to switch current between the SW node and the GND node;

an inductor coupled to conduct current between the SW node and a voltage output (VOUT) node;

a capacitor having a first lead coupled to the VOUT node and a second lead coupled to the GND node;

a third field effect transistor SA having a first terminal, a second terminal and a third terminal, wherein the first terminal of transistor SA is coupled to a voltage input (VIN) node;

a fourth field effect transistor SB having a first terminal, a second terminal and a third terminal, wherein the first terminal of transistor SB is coupled to the second terminal of transistor SA, and wherein the second terminal of transistor SB is coupled to the VOUT node; and

a control circuit that controls the transistor S1, the transistor S2, the transistor SA and the transistor SB such that;

     1) in a charging boost mode transistors SA and SB are turned on and transistors S1 and S2 are pulse-width modulated on and off so that current flows into the power bank circuit via the VIN terminal, through the VIN node, through the transistor SA and through the transistor SB to the VOUT node, and so that an average current flows in the inductor from the VOUT node to the SW node and so that a charging current flows through the transistor S1 and through the VBAT node and to the at least one rechargeable battery so as to charge the at least one rechargeable battery, wherein in the charging boost mode the voltage on the VIN node is always smaller than the VBATL voltage, and wherein in the charging boost mode a current also flows from the VOUT node and through the VOUT terminal and out of the power bank circuit;

     2) in a discharging buck mode transistors SA and SA are turned off and transistors S1 and S2 are pulse-width modulated on and off so that current flows out of the at least one rechargeable battery, through the VBAT node, through the transistor S1 to the SW node, and through the inductor to the VOUT node, and out of the power bank circuit via the VOUT terminal, wherein in the discharging buck mode the voltage on the VBAT node is always higher than the voltage on the VOUT terminal.

2. The power bank circuit of claim 1, wherein the control circuit also controls the transistors S1, S2, SA and SB such that:

3) in a disabled mode transistors SA, SB, S1 and S2 are turned off.

3. The power bank circuit of claim 1, wherein transistors SA and SB are both P-channel field effect transistors.

4. The power bank circuit of claim 1, wherein transistors SA and SB are both N-channel field effect transistors.

5. The power bank circuit of claim 1, wherein the first terminal of transistor SB is a source terminal, and wherein the second terminal of transistor SA is a source terminal.

6. The power bank circuit of claim 1, wherein the first terminal of transistor SB is a drain terminal, and wherein the second terminal of transistor SA is a drain terminal.

7. The power bank circuit of claim 1, wherein transistor SA has a built-in diode, wherein an anode of the built-in diode of transistor SA is coupled to the first terminal of transistor SA, wherein a cathode of the built-in diode of transistor SA is coupled to the second terminal of transistor SA, wherein transistor SB has a built-in diode, wherein a cathode of the built-in diode of transistor SB is coupled to the first terminal of transistor SB, wherein an anode of the built-in diode of transistor SB is coupled to the second terminal of transistor SB.

8. The power bank circuit of claim 1, wherein transistor SA has a built-in diode, wherein a cathode of the built-in diode of transistor SA is coupled to the first terminal of transistor SA, wherein an anode of the built-in diode of transistor SA is coupled to the second terminal of transistor SA, wherein transistor SB has a built-in diode, wherein an anode of the built-in diode of transistor SB is coupled to the first terminal of transistor SB, and wherein a cathode of the built-in diode of transistor SB is coupled to the second terminal of transistor SB.

9. The power bank circuit of claim 1, wherein approximately five volts is present on the VIN terminal when the power bank device is operating in the charging boost mode, wherein said at least one rechargeable battery comprises two series-connected lithium-ion cells, and wherein the voltage VBATL is greater than five volts.

10. The power bank circuit of claim 1, wherein the control circuit and the transistors SA, SB, S1 and S2 are parts of a single integrated circuit, and wherein the inductor and the capacitor are not parts of the integrated circuit.

11. The power bank circuit of claim 1, wherein in the discharging buck mode the transistors S1 and S2 stop switching if the voltage on the VBAT node drops below a predetermined voltage.

12. The power bank circuit of claim 1, wherein in the charging boost mode the transistors S1 and S2 stop switching if the voltage on the VBAT node rises to a predetermined voltage.

13. The power bank circuit of claim 1, wherein the control circuit comprises mode control logic, a pulse-width modulation controller, and a plurality of field effect transistor driver circuits, wherein the mode control logic comprises a state machine, wherein if the state machine is operating in a first state then the control circuit controls the transistors S1, S2, SA and SB to operate in the charging boost mode whereas if the state machine is operating in a second state then the control circuit controls the transistors S1, S2, SA and SB to operate in the discharging buck mode.

14. A method comprising:

(a) in a discharging mode receiving a supply current from at least one battery via a battery voltage (VBAT) terminal of an integrated circuit and switching current through a switch (SW) terminal of the integrated circuit and through an external inductor external to the integrated circuit such that a regulated output voltage VOUT is present on an output node VOUT, wherein the inductor is coupled between the switch (SW) terminal of the integrated circuit and the output node VOUT, wherein a voltage on the VBAT terminal during operation in the discharging mode is greater than the regulated output voltage VOUT, and wherein during operation in the discharging mode the integrated circuit and the external inductor operate as a buck DC-to-DC switching converter; and

(b) in a charging mode receiving a supply current onto an input voltage (VIN) terminal of the integrated circuit and causing a current to flow through the external inductor such that a current-regulated charging current flows out of the VBAT terminal of the integrated circuit and into said at least one battery, wherein during operation in the charging mode a voltage on the VIN terminal is smaller than a voltage on the VBAT terminal, wherein during operation in the charging mode the integrated circuit and the external inductor operate as a boost DC-to-DC switching converter, wherein during operation in the charging mode a current flows from the VIN terminal, through a bypass current path within the integrated circuit, and out of a voltage output (VOUT) terminal of the integrated circuit, and wherein the VOUT terminal of the integrated circuit is coupled to the VOUT output node.

15. The method of claim 14, further comprising:

(c) in a disabled mode preventing any current flow from said at least one battery into the VBAT terminal of the integrated circuit and disabling any switching of current flow either into or out of the SW terminal of the integrated circuit, wherein in the disabled mode the integrated circuit and the external inductor operate neither as a buck DC-to-DC switching converter nor as a boost DC-to-DC switching converter.

16. The method of claim 15, further comprising:

(d) receiving an enable signal onto an enable input terminal of the integrated circuit and in response causing the integrated circuit to stop operating in the disabled mode and to start operating in the discharging mode.

17. The method of claim 14, wherein the integrated circuit comprises a first power transistor S1 coupled to conduct current between the VBAT terminal and the SW terminal, wherein the integrated circuit further comprises a second power transistor S2 coupled to conduct current between the SW terminal and a ground GND terminal of the integrated circuit, wherein the integrated circuit further comprises a third power transistor SA and a fourth power transistor SB that are coupled together in series between the VIN terminal and the VOUT terminal, wherein the transistor SA has a built-in diode, wherein the transistor SB has a built-in diode, and wherein a cathode of the built-in diode of transistor SA is coupled to a cathode of the built-in diode of transistor SB.

18. The method of claim 17, further comprising:

(d) pulse-width modulating the transistors S1 and S2 on and off when the integrated circuit is operating in the discharging mode but controlling the transistors SA and SB to be off when the integrated circuit is operating in the discharging mode;

(e) pulse-width modulating the transistors S1 and S2 on and off when the integrated circuit is operating in the charging mode but controlling the transistors SA and SB to be on when the integrated circuit is operating in the charging mode; and

(f) controlling the transistors S1, S2, SA and SB to be off when the integrated circuit is operating in the disabled mode.

19. A power bank circuit comprising:

a voltage input (VIN) terminal;

a voltage output (VOUT) terminal;

at least one rechargeable battery, wherein the at least one rechargeable battery has an operating voltage range from a fully uncharged operating voltage VBATL to a fully charged operating voltage VBATH, wherein the operating voltage range is between a ground (GND) node and a battery (VBAT) node;

a first field effect transistor S1 coupled to switch current between the VBAT node and a switch (SW) node;

a second field effect transistor S2 coupled to switch current between the SW node and the GND node;

an inductor coupled to conduct current between the SW node and a voltage output (VOUT) node;

a capacitor having a first lead coupled to the VOUT node and a second lead coupled to the GND node;

a third field effect transistor SA having a first terminal, a second terminal and a third terminal, wherein the first terminal of transistor SA is coupled to a voltage input (VIN) node;

a fourth field effect transistor SB having a first terminal, a second terminal and a third terminal, wherein the first terminal of transistor SB is coupled to the second terminal of transistor SA, and wherein the second terminal of transistor SB is coupled to the VOUT node; and

means for controlling the transistor S1, the transistor S2, the transistor SA and the transistor SB such that;

     1) in a charging boost mode transistors SA and SB are turned on and transistors S1 and S2 are pulse-width modulated on and off so that current flows into the power bank circuit via the VIN terminal, through the VIN node, through the transistor SA and through the transistor SB to the VOUT node, and so that an average current flows in the inductor from the VOUT node to the SW node and so that a charging current flows through the transistor S1 and through the VBAT node and to the at least one rechargeable battery so as to charge the at least one rechargeable battery, wherein in the charging boost mode the voltage on the VIN node is always smaller than the VBATL voltage, and wherein in the charging boost mode a current also flows from the VOUT node and through the VOUT terminal and out of the power bank circuit;

     2) in a discharging buck mode transistors SA and SA are turned off and transistors S1 and S2 are pulse-width modulated on and off so that current flows out of the at least one rechargeable battery, through the VBAT node, through the transistor S1 to the SW node, and through the inductor to the VOUT node, and out of the power bank circuit via the VOUT terminal, and wherein in the discharging buck mode the voltage on the VBAT node is always higher than the voltage on the VOUT terminal.

20. The power back circuit of claim 19, wherein the means comprises a mode control logic circuit, a pulse-width modulation controller, and a plurality of transistor drivers, and wherein the mode control logic circuit comprises a state machine.