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Low-Latency Network Interface

  • US 20160269307A1
  • Filed: 03/11/2016
  • Published: 09/15/2016
  • Est. Priority Date: 03/11/2015
  • Status: Active Grant
First Claim
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1. A system comprising:

  • a physical medium attachment (PMA) device configured to generate a bit stream from a signal having encoded data and to shift bits of the bit stream into a shift register until a feedback signal generated by a synchronization decoder is received;

    the synchronization decoder that is connected to an output of the shift register and that is configured to issue the feedback signal to the PMA device whenever the data in the shift register is aligned to a word boundary;

    a descramble code generator configured to generate a descramble code from a clock frequency different than a clock frequency of the output of the shift register of the PMA device, the descramble code generator being configured to provide the descramble code as a first input to a multiplication component;

    a multiplication component configured to digitally multiply a current output of a shift register by the descramble code generated by the descramble code generator;

    a first parallel register configured to receive the output of the multiplication component whenever the synchronization decoder indicates that the data in the shift register is aligned to a word boundary; and

    a second parallel register configured to receive the data from the first parallel register whenever the synchronization decoder determines that the data in the first parallel register is properly aligned.

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