Low-Latency Network Interface
First Claim
1. A system comprising:
- a physical medium attachment (PMA) device configured to generate a bit stream from a signal having encoded data and to shift bits of the bit stream into a shift register until a feedback signal generated by a synchronization decoder is received;
the synchronization decoder that is connected to an output of the shift register and that is configured to issue the feedback signal to the PMA device whenever the data in the shift register is aligned to a word boundary;
a descramble code generator configured to generate a descramble code from a clock frequency different than a clock frequency of the output of the shift register of the PMA device, the descramble code generator being configured to provide the descramble code as a first input to a multiplication component;
a multiplication component configured to digitally multiply a current output of a shift register by the descramble code generated by the descramble code generator;
a first parallel register configured to receive the output of the multiplication component whenever the synchronization decoder indicates that the data in the shift register is aligned to a word boundary; and
a second parallel register configured to receive the data from the first parallel register whenever the synchronization decoder determines that the data in the first parallel register is properly aligned.
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Accused Products
Abstract
Methods, systems, and apparatus for a low-latency network interface. One of the methods includes receiving a signal having encoded data. A bit stream is generated from the received signal. Bits of the bit stream are shifted into a shift register until a feedback signal generated by a synchronization decoder is received. After the feedback signal is received, output of the shift register is descrambled to generate descrambled data. The descrambled data is stored in a first parallel register when the synchronization decoder determines that the data in the shift register is aligned to a word boundary. If the data in the first parallel register is properly aligned, the output is stored in a second parallel register.
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Citations
20 Claims
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1. A system comprising:
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a physical medium attachment (PMA) device configured to generate a bit stream from a signal having encoded data and to shift bits of the bit stream into a shift register until a feedback signal generated by a synchronization decoder is received; the synchronization decoder that is connected to an output of the shift register and that is configured to issue the feedback signal to the PMA device whenever the data in the shift register is aligned to a word boundary; a descramble code generator configured to generate a descramble code from a clock frequency different than a clock frequency of the output of the shift register of the PMA device, the descramble code generator being configured to provide the descramble code as a first input to a multiplication component; a multiplication component configured to digitally multiply a current output of a shift register by the descramble code generated by the descramble code generator; a first parallel register configured to receive the output of the multiplication component whenever the synchronization decoder indicates that the data in the shift register is aligned to a word boundary; and a second parallel register configured to receive the data from the first parallel register whenever the synchronization decoder determines that the data in the first parallel register is properly aligned. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method comprising:
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receiving a signal having encoded data; generating a bit stream from the received signal; shifting bits of the bit stream into a shift register until a feedback signal generated by a synchronization decoder is received; after the feedback signal is received, descrambling output of the shift register to generate descrambled data; storing the descrambled data in a first parallel register when the synchronization decoder determines that the data in the shift register is aligned to a word boundary; determining whether the data in the first parallel register is properly aligned; and storing the output in a second parallel register when the data in the first parallel register is properly aligned. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification