Low-Latency Network Interface

• US 20160269307A1
• Filed: 03/11/2016
• Published: 09/15/2016
• Est. Priority Date: 03/11/2015
• Status: Active Grant

• Current Assignee: Friday Harbor LLC
• Original Assignee: Intellisis Corporation
• Inventors: Kerr, Richard
• Granted Patent: US 9,565,124 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H04L 47/56 implementing delay-aware scheduling
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches

Abstract

Methods, systems, and apparatus for a low-latency network interface. One of the methods includes receiving a signal having encoded data. A bit stream is generated from the received signal. Bits of the bit stream are shifted into a shift register until a feedback signal generated by a synchronization decoder is received. After the feedback signal is received, output of the shift register is descrambled to generate descrambled data. The descrambled data is stored in a first parallel register when the synchronization decoder determines that the data in the shift register is aligned to a word boundary. If the data in the first parallel register is properly aligned, the output is stored in a second parallel register.

Claims

1. A system comprising:

a physical medium attachment (PMA) device configured to generate a bit stream from a signal having encoded data and to shift bits of the bit stream into a shift register until a feedback signal generated by a synchronization decoder is received;

the synchronization decoder that is connected to an output of the shift register and that is configured to issue the feedback signal to the PMA device whenever the data in the shift register is aligned to a word boundary;

a descramble code generator configured to generate a descramble code from a clock frequency different than a clock frequency of the output of the shift register of the PMA device, the descramble code generator being configured to provide the descramble code as a first input to a multiplication component;

a multiplication component configured to digitally multiply a current output of a shift register by the descramble code generated by the descramble code generator;

a first parallel register configured to receive the output of the multiplication component whenever the synchronization decoder indicates that the data in the shift register is aligned to a word boundary; and

a second parallel register configured to receive the data from the first parallel register whenever the synchronization decoder determines that the data in the first parallel register is properly aligned.

2. The system of claim 1, wherein the shift register has a length that is at least as long as code words of the incoming bit stream, and wherein the system is configured to prealign entire code words of the bit stream in the shift register.

3. The system of claim 1, wherein the descramble code generator is configured to operate at a rate slower than a data rate of data output from the shift register of the PMA device.

4. The system of claim 3, wherein the data rate is a multiple of the rate of the descramble code generator.

5. The system of claim 1, wherein the synchronization decoder is configured to operate at a clock rate slower than a data rate of data output from the shift register of the PMA device.

6. The system of claim 5, wherein the data rate is a multiple of the rate of the synchronization decoder.

7. The system of claim 1, wherein the descramble code generator operates outside of the path of data from the shift register to the second parallel register.

8. The system of claim 1, wherein the synchronization decoder operates outside of the path of data from the shift register to the second parallel register.

9. The system of claim 1, wherein the synchronization decoder is configured to send an enable signal to the first parallel register when the output of the shift register is aligned to a word boundary.

10. The system of claim 1, wherein the synchronization decoder is configured to send an enable signal to the second parallel register when the synchronization decoder determines that the data in the first parallel register is properly aligned.

11. A method comprising:

receiving a signal having encoded data;

generating a bit stream from the received signal;

shifting bits of the bit stream into a shift register until a feedback signal generated by a synchronization decoder is received;

after the feedback signal is received, descrambling output of the shift register to generate descrambled data;

storing the descrambled data in a first parallel register when the synchronization decoder determines that the data in the shift register is aligned to a word boundary;

determining whether the data in the first parallel register is properly aligned; and

storing the output in a second parallel register when the data in the first parallel register is properly aligned.

12. The method of claim 11, wherein the shift register has a length that is at least as long as code words of the incoming bit stream, and wherein shifting bits of the bit stream into a shift register until a feedback signal generated by a synchronization decoder is received comprises prealigning entire code words of the bit stream in the shift register.

13. The method of claim 11, wherein descrambling output of the shift register comprises using a descramble code generator that is configured to operate at a rate slower than a data rate of data output from the shift register.

14. The method of claim 13, wherein the data rate is a multiple of the rate of the descramble code generator.

15. The method of claim 13, wherein the descramble code generator operates outside of the path of data from the shift register to the second parallel register.

16. The method of claim 11, wherein the synchronization decoder is configured to operate at a clock rate slower than a data rate of data output from the shift register of the PMA device.

17. The method of claim 16, wherein the data rate is a multiple of the rate of the synchronization decoder.

18. The method of claim 11, wherein the synchronization decoder operates outside of the path of data from the shift register to the second parallel register.

19. The method of claim 11, further comprising sending, by the synchronization decoder, an enable signal to the first parallel register when the output of the shift register is aligned to a word boundary.

20. The method of claim 11, further comprising, sending, by the synchronization decoder, an enable signal to the second parallel register when the synchronization decoder determines that the data in the first parallel register is properly aligned.