DATA STORAGE DEVICES, DATA PROCESSING SYSTEMS HAVING THE SAME, METHODS OF OPERATING AND METHODS OF MANUFACTURING THE SAME

• US 20160274794A1
• Filed: 03/14/2016
• Published: 09/22/2016
• Est. Priority Date: 03/16/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: YOON, Chan Ho
• Granted Patent: US 10,452,269 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 2212/261 Storage comprising a plurality of storage devices
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0605 by facilitating the interaction with a user or administrator
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

A scale-out device to control a group of non-volatile memory devices from among a plurality of non-volatile memory devices at a data storage device, includes a buffer and a scale-out controller. The buffer is configured to store address mapping information for the group of non-volatile memory devices, the group of non-volatile memory devices being a portion of the plurality of non-volatile memory devices at the data storage device. The scale-out controller is configured to control operation of only the group of non-volatile memory devices according to the address mapping information stored at the buffer.

Claims

1. A scale-out device for controlling a group of non-volatile memory devices from among a plurality of non-volatile memory devices at a data storage device, the scale-out device comprising:

a buffer configured to store address mapping information for the group of non-volatile memory devices, the group of non-volatile memory devices being a portion of the plurality of non-volatile memory devices at the data storage device; and

a scale-out controller configured to control operation of only the group of non-volatile memory devices according to the address mapping information stored at the buffer.

2. The scale-out device of claim 1, wherein the address mapping information is logical-to-physical address mapping information for the group of non-volatile memory devices.

3. The scale-out device of claim 1, wherein the buffer is configured to store address mapping information for only the group of non-volatile memory devices from among the plurality of non-volatile memory devices.

4. The scale-out device of claim 1, wherein the scale-out controller is configured to control operation of the group of non-volatile memory devices independently of other non-volatile memory devices among the plurality of non-volatile memory devices at the data storage device.

5. The scale-out device of claim 1, wherein the buffer and the scale-out controller are in the form of a multi-chip package (MCP).

6. The scale-out device of claim 1, wherein the scale-out controller is coupled to the group of non-volatile memory devices through at least a first channel.

7. The scale-out device of claim 6, wherein

the scale-out controller is connected to a first set of non-volatile memory devices, from among the group of non-volatile memory devices, via the first channel;

and

the scale-out controller is connected to a second set of non-volatile memory devices, from among the group of non-volatile memory devices, via a second channel.

8. A memory module comprising:

a first scale-out device coupled, via at least one first channel, to a first group of non-volatile memory devices from among a plurality of non-volatile memory devices, the first scale-out device being configured to

store a first set of address mapping information for the first group of non-volatile memory devices, and

control operation of only non-volatile memory devices in the first group of non-volatile memory devices according to the stored first set of address mapping information.

9. The memory module of claim 8, further comprising:

the first group of non-volatile memory devices.

10. The memory module of claim 9, wherein the first set of address mapping information is logical-to-physical address mapping information for the first group of non-volatile memory devices.

11. The memory module of claim 9, wherein the first scale-out device is configured to store address mapping information for only the first group of non-volatile memory devices.

12. The scale-out device of claim 9, wherein the first scale-out device is in the form of a multi-chip package (MCP).

13. The scale-out device of claim 9, wherein the first group of non-volatile memory devices includes a plurality of first sets of non-volatile memory devices, each first set of non-volatile memory devices being coupled to the first scale-out device via a corresponding one of a plurality of first channels.

14. The memory module of claim 9, further comprising:

a second group of non-volatile memory devices; and

a second scale-out device coupled to the second group of non-volatile memory devices via at least one second channel, the second scale-out device being configured to

store a second set of address mapping information for the second group of non-volatile memory devices, and

control operation of only the second group of non-volatile memory devices according to the stored second set of address mapping information.

16. The memory module of claim 8, further comprising:

a second scale-out device coupled, via at least one second channel, to a second group of non-volatile memory devices from among the plurality of non-volatile memory devices, the second scale-out device being configured to

store a second set of address mapping information for the second group of non-volatile memory devices, and

control operation of only the second group of non-volatile memory devices according to the stored second set of address mapping information.

15. (canceled)

17-19. -19. (canceled)

20. A data storage device comprising:

a memory module including at least a first memory cluster and a first scale-out device, the first memory cluster including at least a first plurality of non-volatile memories, and the first scale-out device having a first local flash translation layer, the first local flash translation layer being configured to associate a first set of logical addresses for the data storage device with a first set of physical addresses, the first set of physical addresses including physical addresses for only the first plurality of non-volatile memories; and

a memory controller having a global flash translation layer configured to associate the first set of logical addresses with the first scale-out device.

21. The data storage device of claim 20, wherein the data storage device is a Universal Flash Storage (UFS) device.

22. The data storage device of claim 20, wherein the first scale-out device comprises:

a buffer configured to store address mapping information for the first set of logical addresses and the first set of physical addresses; and

a scale-out controller configured to control operation of only the first plurality of non-volatile memories according to the address mapping information stored at the buffer.

23. The data storage device of claim 22, wherein the global flash translation layer is configured to associate the first set of logical addresses with the scale-out controller in a table stored at the memory controller.

24. The data storage device of claim 20, wherein the first plurality of non-volatile memories includes a first plurality of groups of non-volatile memory devices, each group of non-volatile memory devices in the first plurality of groups of non-volatile memory devices being coupled to the first scale-out device via a corresponding one of a plurality of first channels.

25-33. -33. (canceled)