MEMORY SYSTEM, COMPUTING SYSTEM INCLUDING THE SAME AND METHOD OF OPERATING MEMORY SYSTEM

• US 20160274917A1
• Filed: 08/18/2015
• Published: 09/22/2016
• Est. Priority Date: 03/16/2015
• Status: Active Grant

• Current Assignee: Mimirip LLC
• Original Assignee: SK Hynix Inc.
• Inventors: PARK, Jong Ju
• Granted Patent: US 10,073,702 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/4403 Processor initialisation

Abstract

Disclosed is a memory system including: a semiconductor memory device; and a memory controller suitable for controlling the semiconductor memory device, and receiving a first command for accessing the semiconductor memory device, and a second command of a different type from that of the first command from a host. The memory controller completes preparation to perform an operation corresponding to the first command by performing a first booting operation when power is up, and outputs a first command ready signal to the host. The memory controller completes preparation to perform an operation corresponding to the second command by performing a second booting operation after the first booting operation, and outputs a second command ready signal to the host.

Claims

1. A memory system comprising:

a semiconductor memory device; and

a memory controller suitable for controlling the semiconductor memory device, and receiving a first command for accessing the semiconductor memory device, and a second command of a different type from that of the first command from a host,

wherein the memory controller completes preparation to perform an operation corresponding to the first command by performing a first booting operation when power is up, and outputs a first command ready signal to the host, and

the memory controller completes preparation to perform an operation corresponding to the second command by performing a second booting operation after the first booting operation, and outputs a second command ready signal to the host.

2. The memory system of claim 1, wherein, when the first command is received from the host after the first command ready signal is output and before the second command ready signal is output, the memory controller performs the operation in response to the first command.

3. The memory system of claim 1, wherein the first command is a read command requesting for reading data stored in the semiconductor memory device.

4. The memory system of claim 1, wherein the memory controller performs the first booting operation by configuring a map table representing a mapping relation between a logical block address and a physical block address by reading map data from a first meta region of the semiconductor memory device.

5. The memory system of claim 1, wherein the second command is a program command requesting for storing data in the semiconductor memory device.

6. The memory system of claim 1, wherein the memory controller performs the second booting operation by determining whether a sudden power off occurs during a program operation of the semiconductor memory device by reading meta information from a second meta region of the semiconductor memory device, and processing a page, on which the program operation is performed, to be invalid based on a determination result.

7. A computing system comprising:

a memory system including a semiconductor memory device; and

a host suitable for transmitting a first command for accessing the semiconductor memory device and a second command of a different type from that of the first command,

wherein the memory system completes preparation to perform an operation corresponding to the first command by performing a first booting operation when power is up, and outputs a first command ready signal to the host, and

the memory system completes preparation to perform an operation corresponding to the second command by performing a second booting operation after the first booting operation, and outputs a second command ready signal to the host.

8. The computing system of claim 7, wherein the host transmits the first command to the memory system after the first command ready signal is received and before the second command ready signal is received.

9. The computing system of claim 7, wherein the memory system performs the operation in response to the first command before outputting the second command ready signal.

10. The computing system of claim 7, wherein the host transmits the second command to the memory system after the second command ready signal is received.

11. The computing system of claim 7, wherein the first command is a read command requesting for reading data stored in the semiconductor memory device.

12. The computing system of claim 7, wherein the memory system further includes a memory controller which performs the first booting operation by configuring a map table representing a mapping relation between a logical block address and a physical block address by reading map data from a first meta region of the semiconductor memory device.

13. The computing system of claim 7, wherein the second command is a program command requesting for storing data in the semiconductor memory device.

14. The computing system of claim 7, wherein the memory system further includes a memory controller that performs the second booting operation by determining whether a sudden power off occurs during a program operation of the semiconductor memory device by reading data from the semiconductor memory device, and processing a page, on which the program operation is performed, to be invalid based on a determination result.

15. A method of operating a memory system in which a memory controller controls a semiconductor memory device and receives a first command and a second command having of different type from that of the first command from a host, the method comprising:

completing preparation to perform an operation corresponding to the first command by performing a first booting operation when power is up;

outputting a first command ready signal to the host when the preparation to perform the operation corresponding to the first command is completed;

completing preparation to perform an operation corresponding to the second command by performing a second booting operation after the second booting operation; and

outputting a second command ready signal to the host when the preparation to perform the operation corresponding to the first command is completed.

16. The method of claim 15, further comprising:

performing the operation in response to the first command when the first command is received from the host after the first command ready signal is output and before the second command ready signal is output.

17. The method of claim 15, wherein the first command is a read command requesting for reading data stored in the semiconductor memory device.

18. The method of claim 15, wherein the second command is a program command requesting for storing data in the semiconductor memory device.

19. The method of claim 15, wherein the performing of the first booting operation comprises:

configuring a map table representing a mapping relation between a logical block address and a physical block address by reading map data from a first meta region of the semiconductor memory device.

20. The method of claim 15, wherein the performing of the second booting operation comprises:

determining whether a sudden power off occurs during a program operation of the semiconductor memory device by reading meta information from a second meta region of the semiconductor memory device; and

processing a page, on which the program operation is performed, to be invalid based on a determination result.