INTEGRATED CIRCUIT USING TOPOLOGY CONFIGURATIONS
First Claim
1. An integrated circuit, comprising:
- a memory array, comprising a plurality of memory cells; and
one or more reconfigurable sense amplifier devices coupled to the memory array and configured to amplify differential voltage levels received from the memory array, the one or more reconfigurable sense amplifier devices comprising;
a plurality of sense amplifier circuits configured to be arranged in one of a plurality of topology configurations, wherein the topology configurations comprise a parallel configuration and a cross parallel configuration; and
one or more switches configured to set the plurality of sense amplifier circuits into the plurality of topological configurations based on one or more control bits.
2 Assignments
0 Petitions
Accused Products
Abstract
Various implementations described herein may refer to and may be directed to circuitry for an integrated circuit using topology configurations. For instance, in one implementation, such circuitry may include a memory array having a plurality of memory cells. Such circuitry may also include one or more reconfigurable sense amplifier devices coupled to the memory array and configured to amplify differential voltage levels received from the memory array. The reconfigurable sense amplifier devices may include a plurality of sense amplifier circuits configured to be arranged in one of a plurality of topology configurations, where the topology configurations include a parallel configuration and a cross parallel configuration. The reconfigurable sense amplifier devices may also include one or more switches configured to set the plurality of sense amplifier circuits into the plurality of topological configurations based on one or more control bits.
-
Citations
20 Claims
-
1. An integrated circuit, comprising:
-
a memory array, comprising a plurality of memory cells; and one or more reconfigurable sense amplifier devices coupled to the memory array and configured to amplify differential voltage levels received from the memory array, the one or more reconfigurable sense amplifier devices comprising; a plurality of sense amplifier circuits configured to be arranged in one of a plurality of topology configurations, wherein the topology configurations comprise a parallel configuration and a cross parallel configuration; and one or more switches configured to set the plurality of sense amplifier circuits into the plurality of topological configurations based on one or more control bits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. An apparatus, comprising:
-
a plurality of integrated circuit devices configured to be arranged in one of a plurality of topology configurations, wherein the topology configurations comprise a parallel configuration and a cross parallel configuration; and one or more switches configured to set the plurality of devices into one of the plurality of topological configuration based on one or more control bits. - View Dependent Claims (12, 13, 14, 15)
-
-
16. An integrated circuit, comprising:
-
a memory array having a plurality of dual port memory cells; a first bit-line pair and a second bit-line pair, wherein each is coupled to a respective dual port memory cell; a first sense amplifier circuit coupled to the first bit-line pair and configured to amplify differential voltage levels received from the respective dual port memory cell; and a second sense amplifier circuit coupled to the second bit-line pair and configured to amplify differential voltage levels received from the respective dual port memory cell, wherein the first sense amplifier circuit and the first bit-line pair or the second sense amplifier circuit and the second bit-line pair are selected to transmit data stored within the respective dual port memory cell during a read operation. - View Dependent Claims (17, 18, 19, 20)
-
Specification