NON-BINARY RANK MULTIPLICATION OF MEMORY MODULE

• US 20160276016A1
• Filed: 11/13/2013
• Published: 09/22/2016
• Est. Priority Date: 11/13/2013
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Inventors: BENEDICT, Melvin K.
• Granted Patent: US 10,522,209 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0623 for memory modules
• CPC Class Codes: G06F 2212/2532 comprising a plurality of modules
• CPC Class Codes: G11C 11/4082 Address Buffers; level conversion circuits
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

One of a plurality of chip select inputs of a load-reduced dual inline memory module (LRDIMM) may be repurposed to an address input. One of a plurality of memory ranks of the LRDIMM may be selected based on a remainder of the plurality of chip select inputs. The repurposed chip select input may be used to support non-binary rank multiplication of the LRDIMM.

Claims

1. A system, comprising:

a repurpose unit to repurpose one of a plurality of chip select inputs of a load-reduced dual inline memory module (LRDIMM) to an address input; and

a select unit to select one of a plurality of memory ranks of the LRDIMM based on a remainder of the plurality of chip select inputs, wherein

the repurposed chip select input is to be used to support non-binary rank multiplication of the LRDIMM.

2. The system of claim 1, wherein,

the LRDIMM includes a plurality of address inputs, and

the select unit is to select one of the plurality of memory ranks of the LRDIMM further based on at least one of the address inputs.

3. The system of claim 2, wherein,

each of the plurality of address inputs relates to a separate bit of an address, and

the repurposed chip select input adds a most significant bit to the address.

4. The system of claim 3, further comprising:

a plurality of the LRDIMMs of claim 1 per channel; and

a memory controller to select one of a plurality of logical ranks via the plurality of chip select inputs and to output the address, wherein

each of the LRDIMMs is to present two of the plurality of logical ranks to the memory controller, and

the memory controller is to provide a different address range for each of the selected logical ranks.

5. The system of claim 1, further comprising:

a buffer to reduce a load on a bus of the LRDIMM, wherein,

the LRDIMM includes a Double data rate (DDR) memory.

6. The system of claim 5, wherein,

the buffer is to be set to a binary rank multiplication number greater than a non-binary rank multiplication supported by the LRDIMM, and

the select unit is to route any memory ranks indicated by the buffer that are not included in the LRDIMM to one of the memory ranks of the LRDIMM.

7. The system of claim 1, wherein,

the repurposed chip select input is to be used to support at least one of 3×

, 5×

, 6× and

7×

rank multiplication of the LRDIMM, and the LRDIMM is to support at least one of 6, 10, 12 and 14 memory ranks.

8. A method, comprising:

receiving, at a load-reduced dual inline memory module (LRDIMM), a plurality of chip select inputs;

repurposing, at the LRDIMM, only one of the chip select inputs to be an address input of an address range; and

selecting one of a plurality of memory ranks of the LRDIMM based on a least a remainder of the chip select inputs, wherein

the repurposed chip select input is to be used to support non-binary rank multiplication of the LRDIMM.

9. The method of claim 8, wherein the selecting further includes selecting one of the plurality of memory ranks of the LRDIMM based on at least a portion of the address range.

10. The method of claim 9, wherein,

the address range includes a plurality of address inputs, each address input to be a bit of the address range, and

the repurposed chip select input is repurposed to be a most significant bit of the address range.

11. The method of claim 9, wherein,

a memory controller is to output the address range to the LRDIMM and to output a chip selection via the plurality of chip select inputs, the chip selection to select one of two logical ranks viewable by the memory controller at the LRDIMM, and

the selecting converts the selected logical rank to one of the plurality of memory ranks.

12. The method of claim 9, wherein,

the non-binary rank multiplication of the LRDIMM includes at least one of 3×

, 5×

, 6× and

7×

rank multiplication, and

the LRDIMM is to support at least one of 6, 10, 12 and 14 memory ranks.

13. A non-transitory computer-readable storage medium storing instructions that, if executed by a processor of a device, cause the processor to:

repurpose one of a plurality of chip select inputs to be one of a plurality of address inputs at a load-reduced dual inline memory module (LRDIMM); and

select one of a plurality of memory ranks of the LRDIMM based on the plurality of chip select inputs and at least one of the plurality of address inputs, wherein

the repurposed chip select input is to be used to support non-binary rank multiplication of the LRDIMM.

14. The non-transitory computer-readable storage medium of claim 13, wherein:

the non-binary rank multiplication of the LRDIMM includes at least one of 3×

, 5×

, 6× and

7×

rank multiplication, and

the LRDIMM is to support at least one of 6, 10, 12 and 14 memory ranks.

15. The non-transitory computer-readable storage medium of claim 13, wherein,

a buffer of the LRDIMM is to be set to a binary rank multiplication number greater than a non-binary rank multiplication supported by the LRDIMM, and

a memory rank indicated by the buffer that is not included in the LRDIMM is at least one of considered invalid and routed to one of the memory ranks of the LRDIMM.

16. The non-transitory computer-readable storage medium of claim 13, wherein,

the LRDIMM includes a plurality of address inputs, and

the select unit is to select one of the plurality of memory ranks of the LRDIMM further based on at least one of the address inputs.

17. The non-transitory computer-readable storage medium of claim 16, wherein,

each of the plurality of address inputs relates to a separate bit of an address, and

the repurposed chip select input adds a most significant bit to the address.

18. The non-transitory computer-readable storage medium of claim 13, wherein to select one of a plurality of memory ranks of the LRDIMM, the instructions cause the processor to select one of the plurality of memory ranks of the LRDIMM based on at least a portion of an address range.

19. The non-transitory computer-readable storage medium of claim 18, wherein,

each address input is a bit of the address range, and

the repurposed chip select input is repurposed to be a most significant bit of the address range.

20. The non-transitory computer-readable storage medium of claim 18, comprising instructions that cause the processor to:

output the address range to the LRDIMM and to output a chip selection via the plurality of chip select inputs, the chip selection to select one of two viewable logical ranks at the LRDIMM, and

convert the selected logical rank to one of the plurality of memory ranks.