NON-BINARY RANK MULTIPLICATION OF MEMORY MODULE
First Claim
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1. A system, comprising:
- a repurpose unit to repurpose one of a plurality of chip select inputs of a load-reduced dual inline memory module (LRDIMM) to an address input; and
a select unit to select one of a plurality of memory ranks of the LRDIMM based on a remainder of the plurality of chip select inputs, whereinthe repurposed chip select input is to be used to support non-binary rank multiplication of the LRDIMM.
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Abstract
One of a plurality of chip select inputs of a load-reduced dual inline memory module (LRDIMM) may be repurposed to an address input. One of a plurality of memory ranks of the LRDIMM may be selected based on a remainder of the plurality of chip select inputs. The repurposed chip select input may be used to support non-binary rank multiplication of the LRDIMM.
10 Citations
20 Claims
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1. A system, comprising:
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a repurpose unit to repurpose one of a plurality of chip select inputs of a load-reduced dual inline memory module (LRDIMM) to an address input; and a select unit to select one of a plurality of memory ranks of the LRDIMM based on a remainder of the plurality of chip select inputs, wherein the repurposed chip select input is to be used to support non-binary rank multiplication of the LRDIMM. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method, comprising:
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receiving, at a load-reduced dual inline memory module (LRDIMM), a plurality of chip select inputs; repurposing, at the LRDIMM, only one of the chip select inputs to be an address input of an address range; and selecting one of a plurality of memory ranks of the LRDIMM based on a least a remainder of the chip select inputs, wherein the repurposed chip select input is to be used to support non-binary rank multiplication of the LRDIMM. - View Dependent Claims (9, 10, 11, 12)
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13. A non-transitory computer-readable storage medium storing instructions that, if executed by a processor of a device, cause the processor to:
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repurpose one of a plurality of chip select inputs to be one of a plurality of address inputs at a load-reduced dual inline memory module (LRDIMM); and select one of a plurality of memory ranks of the LRDIMM based on the plurality of chip select inputs and at least one of the plurality of address inputs, wherein the repurposed chip select input is to be used to support non-binary rank multiplication of the LRDIMM. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification