ULTRATHIN MULTILAYER METAL ALLOY LINER FOR NANO CU INTERCONNECTS

• US 20160276216A1
• Filed: 05/10/2016
• Published: 09/22/2016
• Est. Priority Date: 06/08/2014
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: EDELSTEIN, DANIEL, Grill, Alfred, Knupp, Seth L., Nguyen, Son, Nogami, Takeshi, Paruchuri, Vamsi K., Shobha, Hosadurga K., Yang, Chih-Chao
• Application Number:
  US15/151,260
• Publication Number:
  US 20160276216A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: C23C 16/04 Coating on selected surface areas, e.g. using masks
• CPC Class Codes: C23C 16/06 characterised by the deposition of metallic material
• CPC Class Codes: C23C 16/16 from metal carbonyl compounds
• CPC Class Codes: C23C 16/18 from metallo-organic compounds
• CPC Class Codes: C23C 16/30 Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
• CPC Class Codes: C23C 16/45525 Atomic layer deposition [ALD]
• CPC Class Codes: C23C 16/45544 characterized by the apparatus
• CPC Class Codes: C23C 16/505 using radio frequency discharges
• CPC Class Codes: C23C 16/54 Apparatus specially adapted for continuous coating
• CPC Class Codes: C23C 16/56 After-treatment
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/28568 the conductive layers comprising transition metals H01L21/28518 takes precedence
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/7685 : the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 21/76852 : the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 21/76862 : Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
• CPC Class Codes: H01L 21/76864 : Thermal treatment
• CPC Class Codes: H01L 21/76879 : by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76883 : Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53238 : Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers.

Claims

1-15. -15. (canceled)

16. :

A deposition tool comprising;

a load/unload chamber;

a mechanism for transferring a substrate between said load/unload chamber and a deposition chamber, said deposition chamber connected to said load/unload chamber by a port; and

wherein said deposition chamber is (i) configured to selectively form a metal layer or layers on copper by chemical vapor deposition or by atomic layer deposition and (ii) is configured to form a dielectric layer by chemical vapor deposition, and additionally comprising further downstream chambers selected from at least one of a UV and a Low rf stream plasma or thermal cure means in at least one of a reducing environment ambient to enhance the reaction/intermixing between said layer or layers and said copper.

17. :

The deposition tool of claim 16 having from about 4 to about 5 chambers including a lower chamber, said chambers being employed for depositing multilayer metals, metal alloys and dielectrics and for optionally performing a cure treatment in said lower chamber.