SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

• US 20160276224A1
• Filed: 04/15/2015
• Published: 09/22/2016
• Est. Priority Date: 03/19/2015
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Gan, Tian Choy, Hsiao, Chu-Yun, Hsu, Chia-Fu
• Granted Patent: US 9,698,059 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

The present invention provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first transistor and a second transistor. The first transistor and the second transistor are disposed on the substrate. The first transistor includes a first channel and a first work function layer. The second transistor includes a second channel and a second work function layer, where the first channel and the second channel include different dopants, and the second work function layer and the first work function layer have a same conductive type and different thicknesses.

Claims

1. A method of forming a semiconductor device, comprising:

providing a substrate;

forming a dielectric layer on the substrate, wherein the dielectric layer comprises a first gate trench and a second gate trench formed therein;

performing a first threshold voltage implantation process in the first gate trench;

forming a first work function layer in the first gate trench after the first threshold voltage implantation process; and

forming a second work function layer in the second gate trench, and on the first work function layer in the first gate trench, wherein the first work function layer and the second work function layer have a same conductive type.

2. The method of forming a semiconductor device according to claim 1, further comprising:

performing a second threshold voltage implantation process in the second gate trench before forming the first work function layer, wherein the second threshold voltage implantation process is performed by implanting different dopants from that of the first threshold voltage implantation process.

3. The method of forming a semiconductor device according to claim 1, further comprising:

forming a first dummy gate structure and a second dummy gate structure on the substrate, wherein each of the first dummy gate structure and the second dummy gate structure comprises a dummy gate electrode and an interfacial layer;

removing the dummy gate electrode of the first dummy gate structure to form the first gate trench; and

removing the dummy gate electrode of the second dummy gate structure to form the second gate trench.

4. The method of forming a semiconductor device according to claim 3, further comprising:

removing the interfacial layer of the first dummy gate structure before the first threshold voltage implantation process is performed.

5. The method of forming a semiconductor device according to claim 3, further comprising:

removing the interfacial layer of the first dummy gate structure after the first threshold voltage implantation process is performed.

6. The method of forming a semiconductor device according to claim 1, wherein the first work function layer and the second work function layer comprise different materials or have different thicknesses.

7. The method of forming a semiconductor device according to claim 1, further comprising:

forming a third gate trench in the dielectric layer; and

performing a third threshold voltage implantation process in the third gate trench before forming said first work function layer.

8. The method of forming a semiconductor device according to claim 7, further comprising:

forming a third work function layer in the third gate trench, and on the second work function layer formed in the second gate trench and the first gate trench, wherein the third work function layer has a different conductive type from that of the first work function layer.

9. The method of forming a semiconductor device according to claim 3, further comprising:

forming a fin shaped structure on the substrate, wherein the first dummy gate structure and the second dummy gate structure are formed on the fin shaped structure.

10. A method of forming a semiconductor device, comprising:

providing a substrate;

performing a first threshold voltage implantation process on the entire substrate;

forming a first dummy gate structure and a second dummy gate structure on the substrate, wherein each of the first dummy gate structure and the second dummy gate structure has an interfacial layer and a dummy gate electrode;

removing the dummy gate electrode of the first dummy gate structure to form a first gate trench; and

performing a second threshold voltage implantation process in the first gate trench right after removing the dummy gate electrode of the first dummy gate structure.

11. The method of forming a semiconductor device according to claim 10, wherein the second threshold voltage implantation process is performed by implanting different dopants from that of the first threshold voltage implantation process.

12. The method of forming a semiconductor device according to claim 10, further comprising:

removing the dummy gate electrode of the second dummy gate structure to form a second gate trench; and

performing a third threshold voltage implantation process in the second gate trench right after removing the dummy gate electrode of the second dummy gate structure, wherein the third threshold voltage implantation process is performed by implanting different dopants from that of the first threshold voltage implantation process.

13. The method of forming a semiconductor device according to claim 10, further comprising:

removing the interfacial layer of the first dummy gate structure before the second threshold voltage implantation process is performed.

14. The method of forming a semiconductor device according to claim 10, further comprising:

removing the interfacial layer of the first dummy gate structure after the second threshold voltage implantation process is performed.

15. The method of forming a semiconductor device according to claim 10, further comprising:

forming a fin shaped structure on the substrate, wherein the first dummy gate structure and the second dummy gate structure are formed on the fin shaped structure.

16. A semiconductor device, comprising:

a substrate;

a first gate structure disposed on the substrate, the first gate structure comprising;

a first channel, wherein the first channel comprises different dopant from that of adjacent lightly-doped drain regions and adjacent well region; and

a first work function layer; and

a second gate structure disposed on the substrate, the second gate structure comprising;

a second channel, wherein the second channel comprises different dopant from that of adjacent lightly-doped drain regions and adjacent well region, and the second channel comprises different dopants from that of the first channel; and

a second work function layer, wherein the second work function layer and the first work function layer have a same conductive type and different thicknesses.

17. The semiconductor device according to claim 16, wherein the first work function layer and the second work function layer comprise different materials.

18. The semiconductor device according to claim 16, further comprising:

a third gate structure disposed on the substrate, wherein the third gate structure comprises;

a third channel, wherein the third channel comprises different dopant from that of adjacent lightly-doped drain regions and adjacent well region, and the third channel comprises different dopants from that of the first channel and the second channel; and

a third work function layer, having a conductive type different from that of the first work function layer and the second work function layer.

19. The semiconductor device according to claim 16, wherein the second channel layer and the first channel layer comprise different dopant dosages.

20. The semiconductor device according to claim 16, wherein the second channel layer and the first channel layer comprise different dopant materials.